SiC field effect transistor
A SiC field effect transistor includes: a SiC semiconductor layer; and a MIS transistor structure including a first conductivity type source region in the semiconductor layer, a second conductivity type body region in the semiconductor layer in contact with the source region, a first conductivity type drift region in the semiconductor layer in contact with the body region, a gate electrode opposed to the body region with a gate insulation film interposed between the electrode and the body region for forming a channel in the body region to cause electric current to flow between the drift region and the source region, and a barrier forming layer in contact with the drift region to form a junction barrier by the contact with the drift region, the junction barrier being lower than a diffusion potential of a body diode defined by a junction between the body region and the drift region.
1. A SiC field effect transistor comprising:
a SiC semiconductor layer; and
a Metal Insulator Semiconductor (MIS) transistor structure including
a source region of a first conductivity type provided in the SiC semiconductor layer,
a body region of a second conductivity type provided in the SiC semiconductor layer in contact with the source region,
a drift region of the first conductivity type provided in the SiC semiconductor layer in contact with the body region,
a gate insulation film,
a gate electrode opposed to the body region with the gate insulation film interposed between the gate electrode and the body region for forming a channel in the body region to cause electric current to flow between the drift region and the source region, and
a barrier forming layer provided directly in contact with the drift region to form a junction barrier by the contact with the drift region, the barrier forming layer further being in direct contact with the source region,
wherein the MIS transistor structure includes a vertical MIS transistor structure in which the source region and the drift region are spaced from each other vertically and perpendicularly to a major surface of the SiC semiconductor layer with the body region interposed therebetween,
wherein the vertical MIS transistor structure further includes:
a source trench extending from the major surface of the SiC semiconductor layer to the drift region through the source region and the body region; and
a source electrode provided in contact with the source region, the body region and the drift region in the source trench with the barrier forming layer being disposed in a portion of the source electrode contacting the drift region.
2. The SiC field effect transistor according to claim 1 , wherein the barrier forming layer is made of polysilicon and forms a hetero junction with respect to the drift region.
3. The SiC field effect transistor according to claim 1 , wherein the barrier forming layer is made of a material selected from the group consisting of Ni, Ti, Mo, W and Pt and forms a Schottky junction with respect to the drift region.
4. The SiC field effect transistor according to claim 1 ,
wherein the source electrode includes a polysilicon layer provided in contact with each of the source region, the body region and the drift region,
wherein the polysilicon layer includes
a first portion which forms an ohmic junction with respect to the source region, and
a second portion which serves as the barrier forming layer to form a hetero junction with respect to the drift region.
5. The SiC field effect transistor according to claim 4 ,
wherein the body region has an impurity concentration of not less than 1×10 16 cm −3 .
6. The SiC field effect transistor according to claim 4 ,
wherein the source region has an impurity concentration of not less than 1×10 18 cm −3 .
7. The SiC field effect transistor according to claim 4 ,
wherein the source electrode further includes a metal layer provided on the polysilicon layer,
wherein the metal layer includes a Ti-containing layer provided in a portion thereof contacting the polysilicon layer.
8. The SiC field effect transistor according to claim 1 ,
wherein the source electrode includes:
a polysilicon layer provided in contact with the drift region; and
a metal layer provided on the polysilicon layer in contact with the source region,
wherein the metal layer forms an ohmic junction with respect to the source region,
wherein the polysilicon layer serves as the barrier forming layer to form a hetero junction with respect to the drift region.
9. The SiC field effect transistor according to claim 4 , wherein the polysilicon layer contains at least one impurity selected from the group consisting of N, P, As, Al and B.
10. The SiC field effect transistor according to claim 9 , wherein the polysilicon layer has an impurity concentration of not less than 1×10 15 cm −3 .
11. The SiC field effect transistor according to claim 7 , wherein the metal layer has a structure including a Ti sublayer, a TiN sublayer and an Al sublayer stacked in this order from the polysilicon layer.
12. The SiC field effect transistor according to claim 7 , wherein the metal layer includes a Mo sublayer.
13. The SiC field effect transistor according to claim 1 ,
wherein the vertical MIS transistor structure further includes a gate trench extending from the major surface of the SiC semiconductor layer to the drift region through the source region and the body region,
wherein the vertical MIS transistor structure includes a trench gate type structure in which the gate insulation film is disposed on a side surface of the gate trench and the gate electrode is opposed to the body region with the gate insulation film interposed between the gate electrode and the body region.
14. The SiC field effect transistor according to claim 13 , wherein the source trench has a greater depth than the gate trench.
15. The SiC field effect transistor according to claim 13 , wherein a distance between a side surface of the source trench and the side surface of the gate trench is 0.5 μm to 3 μm.
16. The SiC field effect transistor according to claim 1 , wherein the vertical MIS transistor structure includes a planar gate type structure in which the gate insulation film is disposed on the major surface of the SiC semiconductor layer and the gate electrode is opposed to the body region with the gate insulation film interposed between the gate electrode and the body region.
17. The SiC field effect transistor according to claim 5 ,
wherein the source region has an impurity concentration of not less than 1×10 18 cm −3 .
18. The SiC field effect transistor according to claim 6 ,
wherein the source electrode further includes a metal layer provided on the polysilicon layer,
wherein the metal layer includes a Ti-containing layer provided in a portion thereof contacting the polysilicon layer.
19. The SiC field effect transistor according to claim 5 ,
wherein the source electrode further includes a metal layer provided on the polysilicon layer,
wherein the metal layer includes a Ti-containing layer provided in a portion thereof contacting the polysilicon layer.