Method and system for phase compensation in multi-path communication device
A method and apparatus for a radio base station ( 300 ) aligns IQ data blocks for transmission over multiple radio frequency (RF) signal paths ( 318, 328, 338 ) between a base station controller ( 304 ) and a plurality of antennas ( 340 ) at the base station by determining a path delay ( 317, 327, 337 ) for each RF signal path, and then transmitting IQ data blocks from JESD 204 transmit interfaces ( 301 - 303 ) over each RF signal path ahead of a first predetermined time slot by an advance time period equaling the path delay for each RF signal path, thereby aligning IQ data block signaling to the first predetermined time slot at the antennas.
1. A method for operating a base station comprising a plurality of communication signal paths over a plurality of transceiver front ends to a plurality of antennas at the base station, comprising:
obtaining a plurality of path delay values for the plurality of communication signal paths; and
for each of the plurality of communication signal paths, transmitting one or more data blocks onto said communication signal path ahead of a first predetermined time slot by an advance time period compensating for the path delay value for said communication signal path by:
computing a data delay period from a second predetermined time slot preceding the first predetermined time slot; and
transmitting the one or more data blocks over the first communication signal path upon expiration of the data delay period after the second predetermined time slot and ahead of a first predetermined time slot by the advance time period equaling the path delay for the first communication signal path,
thereby aligning data block signaling over said communication signal path to the first predetermined time slot.
2. The method of claim 1 , where obtaining the plurality of path delay values comprises:
measuring a path delay value for each of the plurality of communication signal paths in the field, or
retrieving a factory-calibrated path delay value for each of the plurality of communication signal paths.
3. The method of claim 1 , further comprising:
generating the one or more data blocks; and
storing the one or more data blocks in a transmit buffer for the first communication signal path ahead of transmitting the one or more data blocks over the first communication signal path by an advance buffer load time period.
4. The method of claim 3 , where storing the one or more data blocks comprises performing a direct memory access store operation from an antenna-carrier (AxC) container to the transmit buffer.
5. The method of claim 1 , where transmitting one or more data blocks comprises transmitting the one or more data blocks over a JESD204-compliant digital interface in advance of the first predetermined time slot by the advance time period.
6. A method for operating a base station comprising a plurality of communication signal paths over a plurality of transceiver front ends and corresponding plurality of antennas at the base station, comprising:
receiving a plurality of digital signals over a corresponding plurality of communication signal paths, each having a receive path delay, where each digital signal comprises a synchronization point; and
retrieving one or more data blocks from each digital signal received over a corresponding communication signal path after a predetermined delay period compensating for the receive path delay for said communication signal path, thereby aligning data block retrieval to the synchronization point of the received digital signal,
where retrieving one or more data blocks comprises:
generating a first phase alignment pulse signal for a first communication signal path which is delayed from the synchronization point by the predetermined delay period; and
providing the first phase alignment pulse signal to a serial interface to trigger buffering of the one or more data blocks received over the first communication signal path after the synchronization point by the predetermined delay period.
7. The method of claim 6 , further comprising obtaining a plurality of receive path delay values corresponding to the plurality of communication signal paths by measuring or retrieving from memory receive path delay values for the plurality of communication signal paths.
8. The method of claim 6 , where providing the first phase alignment pulse signal to the serial interface comprises gating a switch to connect a framer module and FIFO buffer of the serial interface to buffer the one or more data blocks in response to the first phase alignment pulse signal.
9. The method of claim 6 , where a phase control unit programs a receive phase alignment timer to generate the first phase alignment pulse signal.
10. An integrated circuit for a wireless communication device comprising a plurality of radio frequency (RF) signal paths connected between the integrated circuit and a plurality of antennas, each RF signal path having an associated path delay, the integrated circuit comprising:
a plurality of serial data interfaces for transmitting data blocks over a corresponding plurality of RF signal paths to the plurality of antennas; and
a plurality of timers coupled to provide a corresponding plurality of phase alignment signals for controlling the plurality of serial data interfaces, where each timer is configured to generate a phase alignment signal for the corresponding serial data interface in advance of a first predetermined synchronization pulse by an advance time period compensating for a path delay for the RF signal path, where each of the plurality of serial data interfaces comprises a FIFO buffer and a framer coupled to process data blocks from the FIFO buffer in response to a corresponding phase alignment signal.
11. The integrated circuit of claim 10 , where the plurality of timers are configured to provide the corresponding plurality of phase alignment signals so that data block transmission over the plurality of RF signal paths is phase aligned to the first predetermined synchronization pulse.
12. The integrated circuit of claim 10 , where the wireless communication device comprises a base station and where the plurality of serial data interfaces are compliant with a JESD204 standard.
13. The integrated circuit of claim 10 , further comprising: a transmit buffer at each of the plurality of serial data interfaces; and
one or more controllers for storing IQ data blocks in each transmit buffer in response to a plurality of second alignment signals, where each second alignment signal for an RF signal path is generated by a transmit buffer timer ahead of the phase alignment signal for the RF signal path by an advance buffer load time period.
14. An integrated circuit for a wireless communication device comprising a plurality of radio frequency (RF) signal paths connected between a plurality of antennas and the integrated circuit, each RF signal path having an associated path delay, the integrated circuit comprising:
a plurality of receive serial data interfaces for receiving data blocks over a corresponding plurality of RF signal paths from the plurality of antennas, each receive serial data interface comprising a connection switch for connecting a FIFO buffer to receive IQ samples from a deserializer and deframer connected in series to a corresponding antenna; and
a plurality of timers coupled to provide a corresponding plurality of receive alignment signals, each gating a corresponding connection switch in one of the plurality of receive serial data interfaces, where each timer is configured to generate an alignment signal for the corresponding receive serial data interface after a predetermined delay period compensating for the receive path delay for said RF signal path,
where one or more data blocks are retrieved from a digital signal received over a first RF signal path by:
generating at a first timer a first phase alignment pulse signal for the first RF signal path which is delayed from a synchronization point in the digital signal by the predetermined delay period; and
providing the first phase alignment pulse signal to a corresponding receive serial data interface to trigger buffering of the one or more data blocks received over the first RF signal path after the synchronization point by the predetermined delay period.
15. A method for operating a base station comprising a plurality of communication signal paths over a plurality of transceiver front ends to a plurality of antennas at the base station, comprising:
obtaining a plurality of path delay values for the plurality of communication signal paths; and
for each of the plurality of communication signal paths, transmitting one or more data blocks onto said communication signal path ahead of a first predetermined time slot by an advance time period compensating for the path delay value for said communication signal path by:
generating a first phase alignment pulse signal for a first communication signal path in advance of the first predetermined time slot by a first advance time period; and
providing the first phase alignment pulse signal to a serial interface for the first communication signal path to trigger transmission of the one or more data blocks over the first communication signal path in advance of the first predetermined time slot by the first advance time period by gating a switch in a framer module of the serial interface to transmit a lane synchronization sequence over the first communication signal path during a first phase of the first phase alignment pulse signal, and to transmit the one or more data blocks over the first communication signal path during a second phase of the first phase alignment pulse signal,
thereby aligning data block signaling over said communication signal path to the first predetermined time slot.
16. The method of claim 15 , where the lane synchronization sequence comprises zero fill data.
17. The method of claim 15 , where the first predetermined time slot comprises a CPRI synchronization pulse.
18. The method of claim 15 , further comprising programming, in a phase control unit, a transmit phase alignment timer to generate the first phase alignment pulse signal.