Microprocessor mechanism for decompression of cache correction data
An apparatus has a fuse array, a cache memory, and cores. The fuse array is disposed on a die, into which is programmed the configuration data. The fuse array includes a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores compressed cache correction data. The second plurality of fuses stores compressed fuse correction data that indicates locations and values corresponding to one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The cores are disposed on the die, where each of the cores accesses the fuse array upon power-up/reset. The each of the cores includes a cache fuses decompressor that changes the states according to the locations and the values, decompresses the compressed cache correction data, and distributes decompressed cached correction data to initialize the cache memory.
1. An apparatus for providing configuration data to an integrated circuit, the apparatus comprising:
a semiconductor fuse array, disposed on a die, into which is programmed the configuration data, said semiconductor fuse array comprising:
a first plurality of semiconductor fuses, configured to store compressed cache correction data; and
a second plurality of semiconductor fuses, configured to store compressed fuse correction data that indicates locations and values corresponding to one or more fuses within said first plurality of semiconductor fuses whose states are to be changed from that which was previously stored;
a cache memory, disposed on said die; and
a plurality of cores, disposed on said die, wherein each of said plurality of cores is coupled to said semiconductor fuse array and said cache memory, and is configured to access said semiconductor fuse array upon power-up/reset, said each of said plurality of cores comprising:
a cache fuses decompressor, configured to change said states according to said locations and said values, to decompress said compressed cache correction data, and to distribute decompressed cached correction data to initialize said cache memory.
2. The apparatus as recited in claim 1 , wherein said cache fuses decompressor decompresses said compressed cache correction data by executing microcode during power-up/reset.
3. The apparatus as recited in claim 1 , wherein said first plurality of semiconductor fuses comprises a third plurality of semiconductor fuses that indicate one or more sub-unit locations within said cache memory that are not to be employed during normal operation.
4. The apparatus as recited in claim 3 , wherein said first plurality of semiconductor fuses further comprises a fourth plurality of semiconductor fuses that indicate one or more replacement sub-unit locations within said cache memory that are to be employed during normal operation in replacement of corresponding ones of said one or more sub-unit locations.
5. The apparatus as recited in claim 4 , wherein said sub-unit locations and said replacement sub-unit locations comprise columns and redundant columns, respectively, within said cache memory.
6. The apparatus as recited in claim 4 , wherein said sub-unit locations and said replacement sub-unit locations comprise rows and redundant rows, respectively, within said cache memory.
7. The apparatus as recited in claim 1 , wherein the integrated circuit comprises an x86-compatible multi-core microprocessor.
8. An apparatus for reprogramming an integrated circuit device, the apparatus comprising:
a multi-core microprocessor, comprising:
a semiconductor fuse array, disposed on a die, into which is programmed the configuration data, said semiconductor fuse array comprising:
a first plurality of semiconductor fuses, configured to store compressed cache correction data; and
a second plurality of semiconductor fuses, configured to store compressed fuse correction data that indicates locations and values corresponding to one or more fuses within said first plurality of fuses whose states are to be changed from that which was previously stored;
a cache memory, disposed on said die; and
a plurality of cores, disposed on said die, wherein each of said plurality of cores is coupled to said semiconductor fuse array and said cache memory, and is configured to access said semiconductor fuse array upon power-up/reset, said each of said plurality of cores comprising:
a cache fuses decompressor, configured to change said states according to said locations and said values, to decompress said compressed cache correction data, and to distribute decompressed cached correction data to initialize said cache memory.
9. The apparatus as recited in claim 8 , wherein said cache fuses decompressor decompresses said compressed cache correction data by executing microcode during power-up/reset.
10. The apparatus as recited in claim 8 , wherein said first plurality of semiconductor fuses comprises a third plurality of semiconductor fuses that indicates one or more sub-unit locations within said cache memory that are not to be employed during normal operation.
11. The apparatus as recited in claim 10 , wherein said first plurality of semiconductor fuses further comprises a fourth plurality of semiconductor fuses that indicates one or more replacement sub-unit locations within said cache memory that are to be employed during normal operation in replacement of corresponding ones of said one or more sub-unit locations.
12. The apparatus as recited in claim 11 , wherein said sub-unit locations and said replacement sub-unit locations comprise columns and redundant columns, respectively, within said cache memory.
13. The apparatus as recited in claim 11 , wherein said sub-unit locations and said replacement sub-unit locations comprise rows and redundant rows, respectively, within said cache memory.
14. The apparatus as recited in claim 1 , wherein said multi-core microprocessor comprises an x86-compatible multi-core microprocessor.
15. A method for reprogramming an integrated circuit, the method comprising:
first disposing a semiconductor fuse array on a die, the first disposing comprising:
first storing compressed cache correction data in a first plurality of semiconductor fuses; and
second storing fuse correction data in a second plurality of semiconductor fuses, wherein the fuse correction data indicates locations and values corresponding to one or more fuses within the first plurality of semiconductor fuses whose states are to be changed from that which was previously stored;
second disposing a plurality of microprocessor cores on the die, wherein each of the plurality of microprocessor cores is coupled to the semiconductor fuse array and is configured to access all of the compressed cache correction data during power-up/reset, for initialization of elements within the each of the plurality of microprocessor cores; and
via a cache fuses decompressor disposed within the each of the plurality of cores, changing the states according to the locations and the values, decompressing the compressed cache correction data, and distributing decompressed cache correction data to initialize a cache memory.
16. The method as recited in claim 15 , wherein the cache fuses decompressor decompresses the compressed cache correction data by executing microcode during power-up/reset.
17. The method as recited in claim 15 , wherein the first plurality of semiconductor fuses comprises a third plurality of semiconductor fuses that indicates one or more sub-unit locations within the cache memory that are not to be employed during normal operation.
18. The method as recited in claim 17 , wherein the first plurality of semiconductor fuses further comprises a fourth plurality of semiconductor fuses that indicates one or more replacement sub-unit locations within the cache memory that are to be employed during normal operation in replacement of corresponding ones of the one or more sub-unit locations.
19. The method as recited in claim 18 , wherein the sub-unit locations and the replacement sub-unit locations comprise columns and redundant columns, respectively, within the cache memory.
20. The method as recited in claim 18 , wherein the sub-unit locations and the replacement sub-unit locations comprise rows and redundant rows, respectively, within the cache memory.
21. The apparatus as recited in claim 15 , wherein the integrated circuit comprises an x86-compatible multi-core microprocessor.