Structures and methods for making NAND flash memory
A NAND flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell. Gaps etched through such openings may also define peripheral devices.
1. A method of forming a flash memory integrated circuit comprising:
forming a floating gate layer;
forming a dielectric layer on the floating gate layer;
forming a control gate layer on the dielectric layer;
removing portions of the control gate layer and the dielectric layer in opening areas;
subsequently, forming an additional control gate layer such that the additional control gate layer directly overlies the floating gate layer in the opening areas and directly overlies the control gate layer in other areas;
performing a first etch step that etches through the control gate layer, the dielectric layer, and the floating gate layer, to form separate floating gate structures; and
performing a second etch step through opening areas to form separate select gate structures.
2. The method of claim 1 further comprising changing the majority carrier of selected areas of the additional control gate layer and portions of the floating gate layer underlying the selected areas by ion implantation of only the additional control gate layer.
3. The method of claim 1 wherein the second etch step establishes a lateral dimension of a transistor formed in a peripheral area of the flash memory integrated circuit.
4. The method of claim 3 wherein the second etch step further establishes a lateral dimension of a resistor formed in a peripheral area of the flash memory integrated circuit.
5. The method of claim 4 wherein the second etch step further establishes a lateral dimension of at least one plate of a capacitor formed in a peripheral area of the flash memory integrated circuit.
6. The method of claim 5 wherein the capacitor has a capacitor dielectric that is formed from the dielectric layer.
7. The method of claim 5 wherein the capacitor has a capacitor dielectric that is formed from a dielectric material between the floating gate layer and an underlying substrate.
8. The method of claim 7 further comprising removing all material of the dielectric layer in an area where the capacitor is subsequently formed.