Nonvolatile memory device
A nonvolatile memory device includes a first active region and a second active region separated from each other; a floating gate crossing the first active region, and disposed such that an end thereof overlaps with the second active region; a selection gate crossing the first active region, and disposed side by side with and coupled to the floating gate; a dielectric layer disposed between the floating gate and the selection gate, wherein a stack of the dielectric layer, the floating gate and the selection gate forms a first capacitor in a horizontal structure; a well region disposed in the second active region and coupled to the floating gate, wherein a stack of the well region and the floating gate forms a second capacitor in a vertical structure; and a contact commonly coupled to the well region and the selection gate.
1. A nonvolatile memory device comprising:
a first active region and a second active region separated from each other;
a floating gate crossing the first active region, and disposed such that an end thereof overlaps with the second active region;
a selection gate crossing the first active region, disposed side by side, and coupled to the floating gate;
a dielectric layer disposed between the floating gate and the selection gate, wherein a stack of the dielectric layer, the floating gate and the selection gate forms a first capacitor in a horizontal structure;
a well region disposed in the second active region and coupled to the floating gate, wherein a stack of the well region and the floating gate forms a second capacitor in a vertical structure; and
a contact commonly coupled to the well region and the selection gate.
2. The nonvolatile memory device according to claim 1 , wherein the first active region extends in a first direction,
wherein the second active region is separated from the first active region in a second direction, and
wherein the second direction is substantially perpendicular to the first direction.
3. The nonvolatile memory device according to claim 2 , wherein the floating gate and the selection gate are separated from each other in the first direction and are side by side with each other in the second direction.
4. The nonvolatile memory device according to claim 1 , further comprising:
a first junction region, a second junction region and a third junction region disposed in the first active region,
wherein the first junction region and the second junction region are respectively disposed at first and second ends of the first active region,
wherein the first junction region and the second junction region are respectively provided adjacent to sidewalls of the floating gate and the selection gate, and
wherein the third junction region is disposed between the floating gate and the selection gate.
5. The nonvolatile memory device according to claim 4 , wherein the first junction region, the second junction region and the third junction region each have n+ type conductivity.
6. The nonvolatile memory device according to claim 5 , further comprising:
a p type well region disposed to surround the first active region.
7. The nonvolatile memory device according to claim 5 , further comprising:
a p+ type contact region disposed in the second active region.
8. The nonvolatile memory device according to claim 7 , wherein the p+ type contact region is coupled to the contact.
9. The nonvolatile memory device according to claim 4 , wherein the well region has n type conductivity.
10. The nonvolatile memory device according to claim 1 , wherein the first active region and the second active region are defined by an isolation layer.
11. The nonvolatile memory device according to claim 1 , wherein the second capacitor in a vertical structure further comprises an insulation layer disposed between the well region and the floating gate.
12. A nonvolatile memory device comprising:
a charge storage transistor including a floating gate, a first junction region which is coupled to a source line, and a third junction region;
a selection transistor including a selection gate which is coupled to a word line, a second junction region which is coupled to a bit line, and the third junction region which is shared by the charge storage transistor;
a first capacitor component disposed between a terminal of the selection gate and a terminal of the floating gate; and
a diode component and a second capacitor component disposed in series between the terminal of the selection gate and the terminal of the floating gate.
13. The nonvolatile memory device according to claim 12 , wherein the first capacitor component: and the second capacitor component are coupled to each other in parallel between the terminals of the selection gate and the floating gate.
14. The nonvolatile memory device according to claim 12 , further comprising:
a dielectric layer disposed between the floating gate and the selection gate, wherein the first capacitor component includes the floating gate, the dielectric layer and the selection gate.
15. The nonvolatile memory device according to claim 12 , wherein an anode and a cathode of the diode component are respectively coupled to the selection gate and the second capacitor component.
16. The nonvolatile memory device according to claim 14 , further comprising:
a second-conductivity-type contact region coupled to the selection gate,
a first-conductivity-type well region disposed under the floating gate to surround the second-conductivity-type contact region and partially overlap with the floating gate, and
an insulation layer disposed between the first-conductivity-type well region and the floating gate,
wherein the diode component comprises the second-conductivity-type contact region and the first-conductivity-type well region, and wherein the second capacitor component comprises the first-conductivity-type well region, the insulation layer and the floating gate, which are disposed vertically.
17. The nonvolatile memory device according to claim 12 , wherein a bias voltage commonly applied to the word line is coupled to the floating gate by the first capacitor component: and the second capacitor component in such a manner that coupling voltages are induced.
18. The nonvolatile memory device according to claim 17 , wherein programming is performed by applying a positive program voltage and a positive source voltage to the word line and the source line, respectively, and by connecting the bit line to the ground.
19. The nonvolatile memory device according to claim 17 , wherein erasing is performed by applying a negative erase voltage and a positive source voltage to the word line and the source line, respectively, and by connecting the bit line to the ground.
20. The nonvolatile memory device according to claim 17 , wherein reading is performed by applying a positive read voltage and a positive drain voltage to the word line and the bit line, respectively, and by connecting the source line to the ground.