IP Library Granted Patent US 9,224,815
Granted Patent B2
US 9,224,815 · App. 14/147,349 · Granted Dec 29, 2015

Method of tuning doping concentration in III-V compound semiconductor through co-doping donor and acceptor impurities

Inventors: Meng-Ku Chen (New Taipei, TW); Hung-Ta Lin (Hsinhu, TW); Pang-Yen Tsai (Jhu-bei, TW); Huicheng Chang (Tainan, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L29/1054H01L29/66522H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 9,224,815
App. No.
14/147,349
Granted
Dec 29, 2015
Kind
B2
Abstract

A method includes epitaxially growing a first III-V compound semiconductor, wherein the first III-V compound semiconductor is of p-type. The first III-V compound semiconductor is grown using precursors including a first precursor comprising Cp2Mg, and a second precursor comprising a donor impurity. A second III-V compound semiconductor is grown overlying and contacting the first III-V compound semiconductor. The second III-V compound semiconductor is of n-type.

Claims (52)

1. A method comprising:

epitaxially growing a first III-V compound semiconductor, wherein the first III-V compound semiconductor is of p-type, and is grown by simultaneously using precursors comprising:

first precursors comprising a group III element and a group V element;

a second precursor comprising bis cyclopentadienyl magnesium (Cp2Mg); and

a third precursor comprising a donor impurity selected from germanium, tin, selenium, and tellurium.

2. The method of claim 1 , wherein the third precursor comprises silicon, germanium, tin, selenium, or tellurium.

3. The method of claim 1 further comprising;

epitaxially growing a second III-V compound semiconductor overlying and contacting the first III-V compound semiconductor, wherein the second III-V compound semiconductor is of n-type;

forming a gate dielectric over the second III-V compound semiconductor;

forming a gate electrode over the gate dielectric; and

forming a source region and a drain region connected to opposite ends of the second IIIV compound semiconductor, wherein the source region and the drain region are of n-type.

4. The method of claim 3 further comprising:

forming Shallow Trench Isolation (STI) regions in a semiconductor substrate;

removing a portion of the semiconductor substrate between two opposite portions of the STI regions to form a recess, wherein the first III-V compound semiconductor is grown in the recess; and

recessing the STI regions, wherein a portion of the first III-V compound semiconductor over the STI regions forms a fin, and wherein the second III-V compound semiconductor is grown on the fin.

5. A method comprising:

epitaxially growing a first In-V compound semiconductor, wherein during the growing the first In-V compound semiconductor, magnesium and a donor impurity are in-situ codoped;

epitaxially growing a second In-V compound semiconductor overlying and contacting the first In-V compound semiconductor, wherein during the growing the second In-V compound semiconductor, neither the magnesium nor the donor impurity is doped;

forming a gate dielectric over the second In-V compound semiconductor;

forming a gate electrode over the gate dielectric; and

forming a source region and a drain region on opposite ends of the second In-V compound semiconductor, wherein the source region and the drain region are of n-type.

6. The method of claim 5 , wherein the first In-V compound semiconductor is of p-type, and the second In-V compound semiconductor is of n-type.

7. The method of claim 5 , wherein the first In-V compound semiconductor is selected from the group consisting essentially of InP, InAlAs, and combinations thereof, and wherein the second In-V compound semiconductor comprises InGaAs.

8. The method of claim 5 , wherein the first In-V compound semiconductor has a p-type carrier concentration lower than about 1E17 /cm 3 .

9. The method of claim 5 further comprising:

forming Shallow Trench Isolation (STI) regions in a semiconductor substrate;

removing a portion of the semiconductor substrate between two opposite portions of the STI regions to form a recess, wherein the first In-V compound semiconductor is grown in the recess; and

recessing the STI regions, wherein a portion of the first In-V compound semiconductor over the STI regions form a fin, and wherein the second In-V compound semiconductor is grown on the fin.

10. The method of claim 5 , wherein the donor impurity comprises silicon, and wherein in the epitaxially growing the second In-V compound semiconductor, the silicon is supplied through a precursor comprising SiH 4 or Si 2 H 6 .

11. The method of claim 5 , wherein the donor impurity comprises germanium, and wherein in the epitaxially growing the second In-V compound semiconductor, silicon is supplied through a precursor comprising GeH 4 or Ge 2 H 6 .

12. The method of claim 5 further comprising:

forming Shallow Trench Isolation (STI) regions in a semiconductor substrate;

removing a portion of the semiconductor substrate between two opposite portions of the STI regions to form a recess, wherein the first In-V compound semiconductor is grown in the recess; and

recessing the STI regions, wherein a portion of the first In-V compound semiconductor over the STI regions forms a fin, and wherein the second In-V compound semiconductor is grown on the fin.

13. The method of claim 5 , wherein the donor impurity comprises germanium, tin, selenium, or tellurium.

14. A method comprising:

epitaxially growing a first III-V compound semiconductor, wherein the first III-V compound semiconductor is of p-type, and wherein the epitaxially growing the first III-V compound semiconductor is performed using precursors comprising:

a first precursor comprising bis cyclopentadienyl magnesium (Cp2Mg); and

a second precursor comprising a donor impurity;

epitaxially growing a second III-V compound semiconductor overlying and contacting the first III-V compound semiconductor, wherein the second III-V compound semiconductor is of n-type;

forming a gate dielectric over the second III-V compound semiconductor;

forming a gate electrode over the gate dielectric; and

forming a source region and a drain region connected to opposite ends of the second IIIV compound semiconductor, wherein the source region and the drain region are of n-type.

15. The method of claim 14 , wherein during the epitaxially growing the second III-V compound semiconductor, no donor impurity that turns the second III-V compound semiconductor toward n-type is used.

16. The method of claim 14 , wherein during the epitaxially growing the second III-V compound semiconductor, no Cp2Mg is used.

17. The method of claim 14 further comprising:

forming Shallow Trench Isolation (STI) regions in a semiconductor substrate;

removing a portion of the semiconductor substrate between two opposite portions of the STI regions to form a recess, wherein the first III-V compound semiconductor is grown in the recess; and

recessing the STI regions, wherein a portion of the first III-V compound semiconductor over the STI regions forms a fin, and wherein the second III-V compound semiconductor is grown on the fin.

18. The method of claim 14 , wherein the donor impurity comprises silicon, and wherein the second precursor is selected from the group consisting essentially of SiH 4 , Si 2 H 6 , GeH 4 , Ge 2 H 6 , and combinations thereof.

19. The method of claim 14 , wherein the epitaxially growing the first III-V compound semiconductor and the epitaxially growing the second III-V compound semiconductor comprise Metal-Organic Chemical Vapor Deposition (MOCVD).

20. The method of claim 14 , wherein the donor impurity comprises germanium, tin, selenium, or tellurium.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2014
From: CHEN, MENG-KU; LIN, HUNG-TA; TSAI, PANG-YEN; CHANG, HUICHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 031891/0662 →
Continuity (1)
Related Publication 20150194490A1 · Jul 9, 2015