Transistors with wrapped-around gates and methods for forming the same
View Patent ↗A device includes a substrate, a semiconductor strip over the substrate, a gate dielectric wrapping around the semiconductor strip, and a gate electrode wrapping around the gate dielectric. A dielectric region is overlapped by the semiconductor strip. The semiconductor strip and the dielectric region are spaced apart from each other by a bottom portion of the gate dielectric and a bottom portion of the gate electrode.
1. A device comprising:
a substrate;
a semiconductor strip over the substrate, wherein the semiconductor strip comprises silicon and is substantially free from germanium;
a gate dielectric wrapping around the semiconductor strip;
a gate electrode wrapping around the gate dielectric; and
a dielectric region overlapped by the semiconductor strip, wherein the dielectric region comprises silicon germanium oxide, and wherein the semiconductor strip and the dielectric region are spaced apart from each other by a bottom portion of the gate dielectric and a bottom portion of the gate electrode.
2. The device of claim 1 further comprising:
a strip of the substrate, wherein the strip of the substrate is a semiconductor strip, and is overlapped by the dielectric region; and
shallow trench isolation regions on opposite sides of and contacting the strip of the substrate.
3. The device of claim 2 , wherein edges of the dielectric region are substantially aligned to interfaces between the shallow trench isolation regions and the strip of the substrate.
4. The device of claim 1 further comprising a dielectric layer between the gate electrode and the dielectric region, wherein the dielectric layer is formed of a same material as the gate dielectric.
5. The device of claim 4 , wherein the dielectric layer comprises a portion over a top surface of the dielectric region, and portions on sidewalls of the dielectric region.
6. The device of claim 1 , wherein the dielectric region comprises a bottom portion, and sidewall portions over and connected to opposite ends of the bottom portion, and wherein the gate electrode comprises an in-tub portion between opposite sidewall portions of the dielectric region, and wherein the gate dielectric comprises a portion wrapping around the in-tub portion of the gate electrode.
7. A device comprising:
a semiconductor substrate;
a plurality of semiconductor strips over the semiconductor substrate, wherein the plurality of semiconductor strips is parallel to each other and spaced apart from each other;
a plurality of oxide strips underlying and aligned to the plurality of semiconductor strips;
a plurality of insulation regions underlying and aligned to spaces between the plurality of semiconductor strips;
a plurality of strips of the semiconductor substrate underlying and aligned to the plurality of oxide strips, wherein the plurality of strips of the semiconductor substrate is spaced apart from each other by the plurality of insulation regions;
a plurality of gate dielectrics, each wrapping around one of the plurality of semiconductor strips; and
a gate electrode wrapping around the plurality of gate dielectrics, wherein the gate electrode and the plurality of gate dielectrics separate the plurality of semiconductor strips apart from the plurality of oxide strips.
8. The device of claim 7 further comprising a plurality of source regions and a plurality of drain regions on opposite sides of, and connected to, the plurality of semiconductor strips.
9. The device of claim 7 , wherein the plurality of oxide strips comprises top surfaces higher than top surfaces of the plurality of insulation regions.
10. The device of claim 7 , wherein the plurality of oxide strips comprises silicon germanium oxide.
11. The device of claim 7 , wherein each of the plurality of oxide strips comprises:
a bottom portion; and
sidewall portions connected to opposite ends of the bottom portion, wherein the gate dielectric and the gate electrode extend into a space between the sidewall portions of the each of the plurality of oxide strips.
12. The device of claim 7 , wherein the plurality of oxide strips comprises an oxide different from an oxide that can be formed by oxidizing the semiconductor substrate or the plurality of semiconductor strips.
13. A device comprising:
a transistor comprising:
a sub-transistor comprising:
a U-shaped dielectric region comprising a horizontal portion and two vertical portions connected to opposite ends of the horizontal portion, with a space separating the two vertical portions from each other;
a semiconductor region overlapping the space;
a gate dielectric encircling the semiconductor region, wherein the gate dielectric comprises a first portion overlapping the semiconductor region, and a second portion underlying the semiconductor region and extending into the space, and wherein the gate dielectric extends on a top surface and opposite sidewalls of the U-shaped dielectric region; and
a gate electrode encircling the gate dielectric.
14. The device of claim 13 , wherein the U-Shaped dielectric region comprises silicon germanium oxide.
15. The device of claim 13 further comprising:
Shallow Trench Isolation (STI) regions; and
a semiconductor substrate comprising a portion between opposite portions of the STI regions, wherein the space overlaps the portion of the semiconductor substrate.
16. The device of claim 13 , wherein the gate electrode extends into the space.
17. The device of claim 16 , wherein the second portion of the gate dielectric further encircles a portion of the gate electrode extending into the space.
18. The device of claim 13 further comprising:
a plurality of sub-transistor, each comprising:
an additional U-shaped dielectric region comprising an additional horizontal portion and two additional vertical portions connected to opposite ends of the additional horizontal portion, with an additional space separating the two additional vertical portions from each other;
an additional semiconductor region overlapping the additional space;
an additional gate dielectric encircling the additional semiconductor region, wherein the additional gate dielectric comprises a third portion overlapping the additional semiconductor region, and a fourth portion underlying the additional semiconductor region and extending into the additional space; and
an additional gate electrode encircling the additional gate dielectric; and
a source/drain region connected to the semiconductor region of the sub-transistor and the additional semiconductor regions of the plurality of sub-transistors.
19. The device of claim 6 further comprising:
Shallow Trench Isolation (STI) regions, wherein the substrate comprises a portion between opposite portions of the STI regions, and the portion of the substrate is overlapped by the in-tub portion of the gate electrode.
20. The device of claim 6 , wherein the sidewall portions of the dielectric region are higher than the bottom portion of the dielectric region.