IP Library › Granted Patent US 9,225,234
Granted Patent B2
US 9,225,234 · App. 13/843,202 · Granted Dec 29, 2015

In-rush current control for charge-pump LDO

Inventors: I-Ning Ku (Los Angeles, CA); Hui Zheng (Irvine, CA); Xicheng Jiang (Irvine, CA)
Assignee: Broadcom Corporation
H02M1/36G05F1/56H02M3/07
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Quick Facts
Patent No.
US 9,225,234
App. No.
13/843,202
Granted
Dec 29, 2015
Kind
B2
Abstract

A circuit for a charge-pump low-dropout (LDO) regulator may include a comparator circuit configured to control a pass transistor based on an error signal. A pre-charge path may be provided between a supply voltage and an output node of the regulator. The pre-charge path may be configured to allow charging of an output capacitor to a pre-charge voltage during a pre-charge operation mode. The output capacitor may be coupled between the output node of the regulator and ground potential. The pass transistor may be configured to allow charging of the output capacitor during an LDO mode of operation. A charge-pump circuit may be configured to provide a current for charging the output capacitor during the LDO mode of operation.

Claims (68)

1. A circuit for a charge-pump low-dropout (LDO) regulator, the circuit comprising:

a comparator circuit configured to control a pass transistor based on an error signal;

a pre-charge path provided between a supply voltage and an output node of the regulator, the pre-charge path being configured to allow charging of an output capacitor to a pre-charge voltage during a pre-charge operation mode, the output capacitor being coupled between the output node of the regulator and ground potential, wherein the pre-charge path comprises at least one pre-charge switch configured to be in a conducting state during the pre-charge mode of operation;

the pass transistor configured to allow charging of the output capacitor during an LDO mode of operation; and

a charge-pump circuit configured to provide a current for charging the output capacitor during the LDO mode of operation.

2. The circuit of claim 1 , wherein:

the error signal includes a difference between an output voltage of the regulator and a reference signal, and

the at least one pre-charge switch includes an MOS or a BJT transistor.

3. The circuit of claim 2 , wherein:

the at least one pre-charge switch is a small switch, and

one of the at least one pre-charge switch is coupled in parallel to the pass transistor and is configured to be in a conducting state during the pre-charge mode of operation.

4. The circuit of claim 1 , wherein:

the reference voltage is a desired output voltage of the regulator,

the pre-charge voltage is a fraction of the reference voltage, and

the fraction is approximately 80%.

5. The circuit of claim 1 , further comprising a feedback switch coupled between an output of the comparator and a control terminal of the pass transistor, wherein the feedback switch is configured to be in a non-conducting state during the pre-charge mode of operation, and wherein the control terminal of the pass transistor includes a gate terminal of an MOS transistor or a base terminal of a BJT.

6. The circuit of claim 1 , wherein the pre-charge path is configured to drastically reduce an in-rush current passing through the pass transistor during the LDO mode of operation by pre-charging the output capacitor, during the pre-charge mode of operation.

7. The circuit of claim 1 , wherein:

the pass transistor is configured to allow charging of the output capacitor from the pre-charge voltage to the reference voltage, during the LDO mode of operation,

during the LDO mode of operation, the feedback switch is configured in a conducting state to allow the comparator to keep the pass transistor in an active state, and

during the LDO mode of operation, the output voltage of the regulator rises to approximately the same voltage as the reference voltage.

8. The circuit of claim 6 , wherein the charge-pump circuit comprises a fly-back capacitor and a plurality of switches, and the charge-pump circuit is further configured to provide a charging current for the output capacitor during a charge-pump mode of operation.

9. A method for providing a charge-pump low-dropout (LDO) regulator, the method comprising:

configuring a comparator circuit to control a pass transistor based on an error signal;

providing a pre-charge path between a supply voltage and an output node of the regulator, and configuring the pre-charge path to allow charging of an output capacitor to a pre-charge voltage during a pre-charge operation mode, the output capacitor being coupled between the output node of the regulator and ground potential;

configuring the pass transistor to allow charging of the output capacitor during an LDO mode of operation; and

configuring a charge-pump circuit to provide a current for charging the output capacitor during the LDO mode of operation,.

wherein providing the pre-charge path comprises providing at least one pre-charge switch configured to be in a conducting state during the pre-charge mode of operation.

10. The method of claim 9 , wherein:

the error signal includes a difference between an output voltage of the regulator and a reference signal, and

the at least one pre-charge switch includes an MOS or a BJT transistor.

11. The method of claim 10 , wherein the at least one pre-charge switch is a small switch, and

the method further comprises:

coupling one of the at least one pre-charge switch in parallel to the pass transistor; and

configuring the one of the at least one pre-charge switch to be in a conducting state during the pre-charge mode of operation.

12. The method of claim 9 , wherein:

the reference voltage is a desired output voltage of the regulator,

the pre-charge voltage is a fraction of the reference voltage, and

the fraction is approximately 80%.

13. The method of claim 9 , further comprising coupling a feedback switch between an output of the comparator and a control terminal of the pass transistor, and configuring the feedback switch to be in a non-conducting state during the pre-charge mode of operation, and wherein the control terminal of the pass transistor includes a gate terminal of a MOS transistor or a base terminal of a BJT.

14. The method of claim 9 , further comprising pre-charging the output capacitor, during the pre-charge mode of operation, to drastically reduce an in-rush current passing through the pass transistor during the LDO mode of operation.

15. The method of claim 9 , further comprising:

configuring the pass transistor to allow charging of the output capacitor from the pre-charge voltage to the reference voltage, during the LDO mode of operation,

configuring the feedback switch, during the LDO mode of operation, in a conducting state and allowing the comparator to keep the pass transistor in an active state, and

allowing, during the LDO mode of operation, the output voltage of the regulator to rise to approximately the same voltage as the reference voltage.

16. The method of claim 14 , wherein the charge-pump circuit comprises a fly-back capacitor and a plurality of switches, and the method further comprises configuring the charge-pump circuit to provide a charging current for the output capacitor during a charge-pump mode of operation.

17. A power-supply circuit, comprising:

a power source to provide a supply voltage; and

a charge-pump low-dropout (LDO) regulator circuit comprising:

a comparator circuit configured to control a pass transistor based on an error signal;

a pre-charge path provided between a supply voltage and an output node of the regulator, the pre-charge path being configured to allow charging of an output capacitor to a pre-charge voltage during a pre-charge operation mode, the output capacitor being coupled between the output node of the regulator and ground potential, wherein the pre-charge path comprises at least one pre-charge switch configured to be in a conducting state during the pre-charge mode of operation;

the pass transistor configured to allow charging of the output capacitor during an LDO mode of operation; and

a charge-pump circuit configured to provide a current for charging the output capacitor during the LDO mode of operation.

18. The power-supply circuit of claim 17 , wherein:

the error signal includes a difference between an output voltage of the regulator and a reference signal, and

the at least one pre-charge switch includes an MOS or a BJT transistor.

the at least one pre-charge switch is a small switch, and

one of the at least one pre-charge switch is coupled in parallel to the pass transistor and is configured to be in a conducting state during the pre-charge mode of operation.

19. The power-supply circuit of claim 17 , further comprising a feedback switch coupled between an output of the comparator and a control terminal of the pass transistor, wherein:

the feedback switch is configured to be in a non-conducting state during the pre-charge mode of operation,

the control terminal of the pass transistor includes a gate terminal of a MOS transistor or a base terminal of a BJT, and

pre-charging the output capacitor, during the pre-charge mode of operation, drastically reduces an in-rush current passing through the pass transistor during the LDO mode of operation.

20. The power-supply circuit of claim 19 , wherein:

the pass transistor is configured to allow charging of the output capacitor from the pre-charge voltage to the reference voltage, during the LDO mode of operation,

during the LDO mode of operation, the feedback switch is configured in a conducting state to allow the comparator to keep the pass transistor in an active state,

during the LDO mode of operation, the output voltage of the regulator is at approximately the same voltage as the reference voltage,

the charge-pump circuit comprises a fly-back capacitor and a plurality of switches, and

the charge-pump circuit is further configured to provide a charging current for the output capacitor during a charge-pump mode of operation.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2013
From: KU, I-NING; ZHENG, HUI; JIANG, XICHENG
To: BROADCOM CORPORATION
Reel/Frame 030072/0853 →
Continuity (1)
Related Publication 20140266099A1 · Sep 18, 2014