IP Library › Granted Patent US 9,225,248
Granted Patent B2
US 9,225,248 · App. 14/657,200 · Granted Dec 29, 2015

Using a digital delay locked loop synchronous direct current to reduce the electromagnetic interference-wave control method of a DC buck converter and the switching signal

Inventors: Kang Yoon Lee (Seoul, KR); Hong Jin Kim (Seoul, KR); Young Jun Park (Mungyeong-si, KR); Jeong Ah Jang (Seoul, KR); Nak Young Ko (Goyang-si, KR); Dong Hyeon Seo (Incheon, KR)
Assignee: Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
H02M3/158
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Quick Facts
Patent No.
US 9,225,248
App. No.
14/657,200
Granted
Dec 29, 2015
Kind
B2
Abstract

A synchronous direct current (DC)-DC buck converter and a method of controlling the waveforms of switching signals disclosed herein. The synchronous DC-DC buck converter generates a stepped-down output voltage using a first switch configured to apply an input voltage to an inductor and a second switch configured to switch in response to a second switching signal. The synchronous DC-DC buck converter includes a sawtooth generation unit, a driver oscillating signal generation unit, a switching signal generation unit, and a phase tracking unit. The sawtooth generation unit generates a sawtooth wave. The driver oscillating signal generation unit generates an error voltage between the output voltage and a reference voltage, and compares the sawtooth wave with the error voltage, so as to generate a driver oscillating signal. The switching signal generation unit generates each of the first and second switching signals. The phase tracking unit generates the frequency setting signal.

Claims (34)

1. A synchronous direct current (DC)-DC buck converter, the synchronous DC-DC buck converter generating a stepped-down output voltage using a first switch configured to apply an input voltage to an inductor during on-duty time of a first switching signal and a second switch configured to switch in response to a second switching signal complementary to the first switching signal, the synchronous DC-DC buck converter comprising:

a sawtooth generation unit configured to generate a sawtooth wave based on a frequency according to a frequency setting signal;

a driver oscillating signal generation unit configured to generate an error voltage between the output voltage and a reference voltage and to compare the sawtooth wave with the error voltage, so as to generate a driver oscillating signal having a duty ratio corresponding to a magnitude of the error voltage;

a switching signal generation unit configured to generate each of the first and second switching signals to have respectively a waveform obtained by applying dead time to on-duty time of the driver oscillating signal; and

a phase tracking unit configured to generate the frequency setting signal based on a sum signal obtained by summing an active time length signal of a pulse, corresponding to a phase difference between the driver oscillating signal and a reference clock signal, and a frequency variation signal based on a spread spectrum clock setting voltage.

2. The synchronous DC-DC buck converter of claim 1 , wherein:

the switching signal generation unit operates to generate each of the first and second switching signals to have the waveform, obtained by applying the dead time to the on-duty time of the driver oscillating signal, in response to a dead time setting signal; and

the phase tracking unit operates to generate the dead time setting signal based on the sum signal obtained by summing the active time length signal of the pulse, corresponding to the phase difference between the driver oscillating signal and the reference clock signal, and the frequency variation signal based on the spread spectrum clock setting voltage.

3. The synchronous DC-DC buck converter of claim 2 , wherein the phase tracking unit comprises:

a pulse generation unit configured to generate a pulse corresponding to a phase difference between a divided signal, obtained by dividing the driver oscillating signal at a predetermined division ratio, and the reference clock signal;

a time-to-digital converter configured to generate the active time length signal in accordance with a length of an active interval of the generated pulse;

a spread spectrum clock control unit configured to generate the frequency variation signal based on the spread spectrum clock setting voltage;

a summing unit configured to generate the sum signal by summing the active time length signal and the frequency variation signal; and

a digital loop filter configured to filter the sum signal, to determine a magnitude of the frequency setting signal in proportion to a magnitude of the filtered sum signal, and to determine a magnitude of the dead time setting signal in inverse proportion to the magnitude of the filtered sum signal.

4. The synchronous DC-DC buck converter of claim 2 , wherein:

the frequency setting signal is set to vary a frequency of the sawtooth wave in proportion to the spread spectrum clock setting voltage; and

the dead time setting signal is set to vary the dead time length in inverse proportion to the spread spectrum clock setting voltage.

5. A method of controlling switching control waveforms of a synchronous DC-DC buck converter, the synchronous DC-DC buck converter generating a stepped-down output voltage using a first switch configured to apply an input voltage to an inductor during on-duty time of a first switching signal and a second switch configured to switch in response to a second switching signal complementary to the first switching signal, the method comprising:

generating a sawtooth wave based on a frequency according to a frequency setting signal;

generating an error voltage between the output voltage and a reference voltage, and comparing the sawtooth wave with the error voltage, so as to generate a driver oscillating signal having a duty ratio corresponding to a magnitude of the error voltage;

generating each of the first and second switching signals to have a waveform obtained by applying dead time to on-duty time of the driver oscillating signal; and

generating the frequency setting signal based on a sum signal obtained by summing an active time length signal of a pulse, corresponding to a phase difference between the driver oscillating signal and a reference clock signal, and a frequency variation signal based on a spread spectrum clock setting voltage.

6. The method of claim 5 , wherein:

generating each of the first and second switching signals comprises generating each of the first and second switching signals to have the waveform, obtained by applying the dead time to the on-duty time of the driver oscillating signal, in response to a dead time setting signal; and

the method further comprises generating the dead time setting signal based on the sum signal obtained by summing the active time length signal of the pulse, corresponding to the phase difference between the driver oscillating signal and the reference clock signal, and the frequency variation signal based on the spread spectrum clock setting voltage.

7. The method of claim 6 , wherein generating the frequency setting signal and generating the dead time setting signal comprise:

generating a pulse corresponding to a phase difference between a divided signal, obtained by dividing the driver oscillating signal at a predetermined division ratio, and the reference clock signal;

generating the active time length signal in accordance with a length of an active interval of the generated pulse;

generating the frequency variation signal based on the spread spectrum clock setting voltage;

generating the sum signal by summing the active time length signal and the frequency variation signal; and

filtering the sum signal, determining a magnitude of the frequency setting signal in proportion to a magnitude of the filtered sum signal, and determining a magnitude of the dead time setting signal in inverse proportion to the magnitude of the filtered sum signal.

8. The method of claim 6 , wherein:

the frequency setting signal is set to vary a frequency of the sawtooth wave in proportion to the spread spectrum clock setting voltage; and

the dead time setting signal is set to vary the dead time length in inverse proportion to the spread spectrum clock setting voltage.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2015
From: LEE, KANG YOON; KIM, HONG JIN; PARK, YOUNG JUN; JANG, JEONG AH; KO, NAK YOUNG; SEO, DONG HYEON
To: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
Reel/Frame 036436/0573 →
Priority Claims (1)
KR 10-2014-0030622 · Mar 14, 2014 · national
Continuity (1)
Related Publication 20150263625A1 · Sep 17, 2015