Capless on chip voltage regulator using adaptive bulk bias

1. An integrated circuit die comprising:

an FDSOI semiconductor substrate including:

a first layer of semiconductor material;

a buried dielectric layer positioned on the first layer of semiconductor material; and

a second layer of semiconductor material positioned on the buried dielectric layer;

an output node that supplies an output voltage;

an output transistor that supplies an output current to the output node;

a feedback loop coupled to the output transistor, wherein the feedback loop regulates the output voltage by generating a loop current based on the output current, the feedback loop including a first loop transistor having a control gate and a back gate, the back gate of the first loop transistor being implemented in the first layer of semiconductor material; and

an adaptive bias generator coupled to the feedback loop, wherein the adaptive bias generator applies a back gate bias voltage to the back gate of the first loop transistor and adapts a ratio of the loop current and the output current by adjusting the back gate bias voltage based on the output current.

2. The integrated circuit die of claim 1 wherein the control gate of the first loop transistor is positioned above the second layer of semiconductor material.

3. The integrated circuit die of claim 2 wherein the feedback loop includes a second loop transistor having a control gate coupled to the control gate of the first loop transistor and a back gate coupled to the back gate of the first loop transistor.

4. The integrated circuit die of claim 3 wherein the output transistor has a control gate coupled to the control gates of the first and second loop transistors.

5. The integrated circuit die of claim 4 wherein the adaptive bias generator compares the loop current to a reference current and generates the back gate bias voltage based on the comparison between the loop current and the reference current.

6. The integrated circuit die of claim 5 wherein the adaptive bias generator receives a mirrored current based on the loop current and compares the loop current to the reference current by comparing the mirrored current to the reference current.

7. The integrated circuit die of claim 3 wherein the first loop transistor has a source terminal coupled to the output node and the second loop transistor has a source terminal coupled to a reference voltage generator.

8. The integrated circuit die of claim 7 comprising a current subtractor coupled to the source terminal of the second loop transistor and configured to pass a portion of the loop current.

9. The integrated circuit die of claim 1 wherein the feedback loop is a positive feedback loop having a gain less than 1.

10. The integrated circuit die of claim 1 including a capacitor coupled between the output node and ground.

11. A method comprising:

passing a load current through an output transistor to an output node; and

regulating an output voltage on the output node by;

supplying a reference voltage to a feedback loop coupled to the output transistor;

generating a loop current in the feedback loop based on the load current;

applying a back gate bias voltage to a back gate of a first loop transistor of the feedback loop; and

adapting a ratio of the loop current and the load current by adjusting the back gate bias voltage based on the loop current.

12. The method of claim 11 comprising:

comparing the loop current to a reference current; and

adapting the back gate bias voltage based on the comparison between the loop current and the reference current.

13. The method of claim 12 wherein comparing the loop current to the reference current includes comparing the reference current to a mirrored current based on the loop current.

14. The method of claim 13 comprising applying the back gate bias voltage to a back gate of a second loop transistor of the feedback loop.

15. The method of claim 14 wherein the first and second loop transistors are NMOS transistors.

16. The method of claim 15 comprising:

generating the loop current with the first loop transistor; and

regulating the output voltage with the second loop transistor.

17. The method of claim 16 wherein a control gate of the first loop transistor is coupled to a control gate of the second loop transistor.

18. The method of claim 15 wherein adapting the back gate bias voltage includes:

increasing the back gate bias voltage as the loop current decreases; and

decreasing the back gate bias voltage as the loop current increases.

19. A device comprising:

an output node that supplies an output voltage;

an output transistor that passes a first current to the output node;

a reference voltage node that outputs a reference voltage;

a feedback loop coupled to the output node and the reference voltage node and that generates a second current based on the first current and that regulates the output voltage by applying a control signal to a gate terminal of the output transistor based on the reference voltage and the second current; and

an adaptive bias generator that adjusts a ratio of the first and second currents based on a comparison of the second current to a reference current.

20. The device of claim 19 comprising an FDSOI semiconductor substrate including:

a first layer of semiconductor material;

a buried dielectric layer positioned on the first layer of semiconductor material; and

a second layer of semiconductor material positioned on the buried dielectric layer.

21. The device of claim 20 wherein the feedback loop includes a loop transistor having:

a control gate coupled to a control gate of a pass transistor; and

a back gate positioned in the second layer of semiconductor material, wherein the adaptive bias generator applies a back gate bias voltage to the back gate of the loop transistor and adjusts the ratio of the first and second currents by adjusting the back gate bias voltage.