Mechanisms for forming radio frequency (RF) area of integrated circuit structure
Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region.
1. A radio frequency area of an integrated circuit structure, comprising:
a substrate;
a buried oxide layer formed over the substrate, wherein an interface layer is formed between the substrate and the buried oxide layer;
a silicon layer formed over the buried oxide layer;
an interlayer dielectric layer formed in a deep trench, wherein the interlayer dielectric layer extends through the silicon layer, the buried oxide layer and the interface layer;
an implant region formed below the interlayer dielectric layer inside the deep trench; and
a polysilicon layer formed below the implant region, wherein the overall region of the polysilicon layer is formed below the implant region, and wherein a top surface of the implant region is level with a bottom surface of the interface layer.
2. The radio frequency area of an integrated circuit structure as claimed in claim 1 , a first resistance of the substrate is higher than a second resistance of the interface layer.
3. The radio frequency area of an integrated circuit structure as claimed in claim 2 , wherein the first resistance is in a range from about 750 to about 10000 ohms-centimeter.
4. The radio frequency area of an integrated circuit structure as claimed in claim 1 , wherein the interface layer is inhomogeneous.
5. The radio frequency area of an integrated circuit structure as claimed in claim 1 , wherein the deep trench has a depth in a range from 0.5 um to 10 um.
6. The radio frequency area of an integrated circuit structure as claimed in claim 1 , wherein the deep trench has a width in a range from 0.5 um to 100 um.
7. The radio frequency area of an integrated circuit structure as claimed in claim 1 , wherein a sum of a thickness of the implant region and a thickness of the polysilicon layer is in a range from 10 A to 10000 A.
8. The radio frequency area of an integrated circuit structure as claimed in claim 7 , wherein a ratio of the thickness of the polysilicon layer to the sum of the thickness of the implant region and the polysilicon layer is in a range from 10% to about 90%.
9. The radio frequency area of an integrated circuit structure as claimed in claim 1 , further comprising:
a shallow trench isolation (STI) region formed on the substrate, wherein the STI region is surrounded by the silicon layer.
10. The radio frequency area of an integrated circuit structure as claimed in claim 9 , wherein the STI region and the silicon layer are arranged in a regular pattern, and the pattern comprises a square, circular, or rectangular shape.
11. The radio frequency area of an integrated circuit structure as claimed in claim 10 , wherein the implant region is formed between two adjacent patterns to form a fence-like shape.
12. A radio frequency area of an integrated circuit structure, comprising:
a substrate having a first resistance;
a buried oxide layer formed over the substrate;
an interface layer formed between the substrate and the buried oxide layer, wherein the interface layer has a second resistance lower than the first resistance;
a silicon layer formed over the buried oxide layer;
an interlayer dielectric layer formed in a deep trench, wherein the interlayer dielectric layer extends through the silicon layer, the buried oxide layer and the interface layer;
an implant region formed in the substrate and below the interlayer dielectric layer, wherein the implant region is inside the deep trench; and
a polysilicon layer formed below the implant region, wherein the overall region of the polysilicon layer is formed below the implant region, and wherein a top surface of the implant region is level with a bottom surface of the interface layer.
13. The radio frequency area of an integrated circuit structure as claimed in claim 12 , wherein opposing portions of the interface layer are separated from each other by at least one of the interlayer dielectric layer in the deep trench and the implant region in the substrate.
14. The radio frequency area of an integrated circuit structure as claimed in claim 12 , further comprising:
a shallow trench isolation (STI) region formed on the substrate, wherein the STI region is surrounded by the silicon layer.
15. The radio frequency area of an integrated circuit structure as claimed in claim 12 , further comprising:
at least one of a resistor, a capacitor and an inductor formed over the interlayer dielectric layer.
16. The radio frequency area of an integrated circuit structure as claimed in claim 12 , wherein the deep trench has a depth in a range from 0.5 um to 10 um.
17. The radio frequency area of an integrated circuit structure as claimed in claim 12 , wherein the overall area of integrated circuit is occupied by the implant region, except for a resistor region and a field-effect transistor (FET) region.
18. The radio frequency area of an integrated circuit structure as claimed in claim 12 , wherein the interface layer is inhomogeneous.
19. The radio frequency area of an integrated circuit structure as claimed in claim 12 , wherein a ratio of the thickness of the polysilicon layer to the sum of the thickness of the implant region and the polysilicon layer is in a range from 10% to about 90%.
20. The radio frequency area of an integrated circuit structure as claimed in claim 14 , wherein the STI region and the silicon layer are arranged in a regular pattern, and the pattern comprises a square, circular, or rectangular shape.