Semiconductor device having vertical channel
A vertical-channel semiconductor device includes an active pillar including a channel region, a gate located at a sidewall of the active pillar, a buried bit-line formed below the active pillar, and an insulation film formed below the buried bit-line. Some parts of the buried bit-line are replaced with an insulation film, such that a bit-line junction leakage is prevented.
1. A vertical-channel semiconductor device comprising:
first and second active pillars each including a channel region;
a first buried bit-line disposed below the first active pillar;
a first upper impurity region disposed between the channel region and the first buried bit-line;
a first lower impurity region disposed below the first buried bit-line and having a smaller width than the first upper impurity region;
a second buried bit-line disposed below the second active pillar;
a second upper impurity region disposed between the channel region and the second buried bit-line;
a second lower impurity region disposed below the second buried bit-line and having a smaller width than the second upper impurity region; and
an insulation film disposed between the first buried bit-line and the second buried bit-line,
wherein the insulation film extends below the first buried bit-line, extends below the second buried bit-line, or extends below both the first buried bit-line and the second buried bit-line, and
wherein the first lower impurity region is vertically aligned with a center portion of the first buried bit-line and the second lower impurity region is vertically aligned with a center portion of the second buried bit-line.
2. The vertical-channel semiconductor device according to claim 1 , further comprising:
a first gate pad located at a first side of the first active pillar;
a second gate pad located at a second side of the first active pillar and at a first side of the second active pillar;
a third gate pad located at a second side of the second active pillar;
first to third gate contacts disposed over the corresponding gate pads and respectively coupled to the first to third gate pads; and
a word line extending across the first and second buried bit-lines, and coupled to the first to third gate contacts.
3. The vertical-channel semiconductor device according to claim 2 , wherein the first to third gate pads are arranged in a same direction as the word line.
4. The vertical-channel semiconductor device according to claim 2 , wherein the first to third gate pads include a stacked structure of a barrier metal film and a tungsten film.
5. The vertical-channel semiconductor device according to claim 2 , wherein the first active pillar is disposed between the first gate contact and the second gate contact, and the second active pillar is disposed between the second gate contact and the third gate contact.
6. The vertical-channel semiconductor device according to claim 1 , wherein the first and second buried bit-lines include a cobalt silicide (CoSi 2 ) material.
7. The vertical-channel semiconductor device according to claim 1 , further comprising an air-gap formed in the insulation film.
8. A vertical-channel semiconductor device comprising:
an active pillar including a channel region;
a gate located at a first sidewall of the active pillar;
a buried bit-line disposed below the active pillar;
a first impurity region disposed between the channel region and the buried bit-line;
a second impurity region disposed below the buried bit-line and having a smaller width than the first impurity region; and
an insulation film extending below the gate to below the buried bit-line,
wherein the second impurity region is vertically aligned with a center portion of the buried bit line.
9. The vertical-channel semiconductor device according to claim 8 , wherein the insulation film extends symmetrically with respect to the gate below the buried bit line and a neighboring buried bit line.
10. The vertical-channel semiconductor device according to claim 8 , wherein the gate includes:
a first gate pad disposed at a second sidewall of the active pillar; and
a second gate pad disposed at a third sidewall of the active pillar in such a manner that the second gate pad is isolated from the first gate pad.
11. The vertical-channel semiconductor device according to claim 10 , further comprising:
a first gate contact disposed over the first gate pad and coupled to the first gate pad;
a second gate contact disposed over the second gate pad and coupled to the second gate pad; and
a word line coupled to the first gate contact and the second gate contact.
12. The vertical-channel semiconductor device according to claim 11 , wherein the active pillar is disposed between the first gate contact and the second gate contact.
13. The vertical-channel semiconductor device according to claim 8 , wherein the buried bit-line includes a cobalt silicide (CoSi 2 ) material.
14. The vertical-channel semiconductor device according to claim 8 , further comprising:
an air-gap disposed at both sides of the buried bit-line.