Semiconductor device and fabricating method thereof
View Patent ↗A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure.
1. A semiconductor device, comprising:
a substrate;
a gate structure over the substrate comprising:
a gate dielectric layer over the substrate;
a gate electrode over the gate dielectric layer;
an isolation layer over the gate electrode; and
a spacer next to each of the two sides of the gate electrode;
a source/drain regions adjacent to the pair of spacers in the substrate;
an etch stop layer next to the pair of spacers and overlying the substrate;
a contact plug extending into the source/drain region and partially overlapping the gate structure through the spacer;
a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the spacer without the contact plug; and
an interlayer dielectric layer over the protective layer.
2. The semiconductor device of claim 1 , wherein a refractive index of a material of the interlayer dielectric layer is in a range from about 2.5 to about 4.
3. The semiconductor device of claim 2 , wherein the material of the interlayer dielectric layer is flowable oxide.
4. The semiconductor device of claim 1 , wherein the gate electrode is metal electrode and the gate dielectric layer is high-k dielectric layer.
5. The semiconductor device of claim 1 , wherein a refractive index of a material of the protective layer is in a range from about 1.4 to about 2.
6. The semiconductor device of claim 5 , wherein the material of the protective layer is selected from the group consisting of SiON, SiOCN, and SiO 2 .
7. The semiconductor device of claim 1 , wherein a thickness of the protective layer is in a range from about 1 nm to about 5 nm.
8. The semiconductor device of claim 1 , wherein a thickness of the etch stop layer is in a range from about 1 nm to about 15 nm.
9. The semiconductor device of claim 1 , wherein a material of the etch stop layer comprises Si 3 N 4 or SiN.
10. The semiconductor device of claim 1 , wherein a material of the isolation layer comprises SiN.
11. The semiconductor device of claim 1 , wherein a thickness of the etch stop layer is thinner than that of the isolation layer.
12. A semiconductor device, comprising:
a substrate;
a gate structure over the substrate comprising:
a gate electrode over the gate dielectric layer;
an isolation layer over the gate electrode; and
a spacer next to each of the two sides of the gate electrode;
a source/drain regions adjacent to the pair of spacers in the substrate;
an etch stop layer next to the pair of spacers and overlying the substrate;
a contact plug extending into the source/drain region and partially overlapping the gate structure through the spacer;
a protective layer over the etch stop layer overlying the substrate; and
an interlayer dielectric layer over the protective layer.
13. The semiconductor device of claim 12 , wherein a material of the protective layer is selected from the group consisting of SiON, SiOCN, and SiO 2 .
14. The semiconductor device of claim 12 , wherein a thickness of the protective layer is in a range from about 1 nm to about 5 nm.
15. The semiconductor device of claim 12 , wherein a thickness of the etch stop layer is in a range from about 1 nm to about 15 nm.
16. The method of claim 12 , wherein a refractive index of a material of the interlayer dielectric layer is in a range from about 2.5 to about 4.
17. The method of claim 16 , wherein the material of the interlayer dielectric layer is flowable oxide.
18. The method of claim 12 , wherein the gate electrode is metal electrode and the gate dielectric layer is high-k dielectric layer.
19. The method of claim 12 , wherein a refractive index of a material of the protective layer is in a range from about 1.4 to about 2.
20. The method of claim 12 , wherein a thickness of the etch stop layer is thinner than that of the isolation layer.