Mechanism for forming metal gate structure
Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively. The semiconductor device further includes a metal gate stack formed over the semiconductor substrate and between the source region and the drain region. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively. The semiconductor device includes a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions. The semiconductor device includes contact plugs formed in the contact openings.
1. A semiconductor device, comprising:
a semiconductor substrate, wherein a source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively;
a metal gate stack formed over the semiconductor substrate and between the source region and the drain region, wherein the metal gate stack comprises a gate electrode and a work function metal layer, and the work function metal layer covers a sidewall and a bottom surface of the gate electrode;
an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively, and a first pre-amorphized implantation element is implanted in the metal silicide regions and the insulating layer adjacent to the contact openings, wherein the first pre-amorphized implantation element includes phosphorus (P), xenon (Xe), carbon (C), germanium (Ge), boron fluoride (BF 2 ), arsenic (As), or fluorine (F);
a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions, and a second pre-amorphized implantation element is implanted in the metal silicide regions and the dielectric spacer liner layer; and
contact plugs formed in the contact openings.
2. The semiconductor device as claimed in claim 1 , wherein a width of the metal silicide region is larger than a diameter of the contact opening.
3. The semiconductor device as claimed in claim 2 , wherein a ratio of the width of the metal silicide region to the diameter of the contact opening ranges from about 1.3 to about 2.3.
4. The semiconductor device as claimed in claim 1 , wherein a width of the metal silicide region is larger than a thickness of the metal silicide region.
5. The semiconductor device as claimed in claim 4 , wherein a ratio of the width to the thickness of the metal silicide region is in a range from about 1.5 to about 2.5.
6. The semiconductor device as claimed in claim 1 , wherein a width of the metal silicide region is larger than a width of the contact plug.
7. The semiconductor device as claimed in claim 1 , wherein the dielectric spacer liner layer is in direct contact with the metal silicide regions.
8. The semiconductor device as claimed in claim 1 , further comprising:
stressors formed in the source region and the drain region, respectively, wherein the metal silicide regions are formed in the stressors.
9. The semiconductor device as claimed in claim 1 , wherein the contact plugs electrically connect the metal silicide regions.
10. The semiconductor device as claimed in claim 1 , wherein the metal silicide regions are made of a silicide material of a metal material, and the metal material comprises nickel, cobalt, platinum, titanium, ytterbium, molybdenum, or erbium.
11. A semiconductor device, comprising:
a semiconductor substrate, wherein a source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively;
a metal gate stack formed over the semiconductor substrate and between the source region and the drain region, wherein the metal gate stack comprises a gate electrode and a work function metal layer, and the work function metal layer covers a sidewall and a bottom surface of the gate electrode;
an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing a portion of top surfaces of the metal silicide regions, respectively, and a first pre-amorphized implantation element is implanted in the metal silicide regions and the insulating layer adjacent to the contact openings, wherein the first pre-amorphized implantation element includes phosphorus (P), xenon (Xe), carbon (C), germanium (Ge), boron fluoride (BF 2 ), arsenic (As), or fluorine (F);
a dielectric spacer liner layer formed over inner walls of the contact openings, wherein a second pre-amorphized implantation element is implanted in the metal silicide regions and the dielectric spacer liner layer; and
contact plugs formed in the contact openings.
12. The semiconductor device as claimed in claim 11 , wherein a ratio of a width of the metal silicide region to a diameter of the contact opening ranges from about 1.3 to about 2.3.
13. The semiconductor device as claimed in claim 11 , wherein a ratio of a width to a thickness of the metal silicide region is in a range from about 1.5 to about 2.5.
14. The semiconductor device as claimed in claim 11 , wherein a width of the metal silicide region is larger than a width of the contact plug.
15. The semiconductor device as claimed in claim 11 , wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions.
16. The semiconductor device as claimed in claim 11 , wherein a width of the metal silicide region is larger than a diameter of the contact opening.
17. The semiconductor device as claimed in claim 11 , wherein a width of the metal silicide region is larger than a thickness of the metal silicide region.
18. The semiconductor device as claimed in claim 11 , wherein the dielectric spacer liner layer is in direct contact with the metal silicide regions.
19. The semiconductor device as claimed in claim 11 , further comprising:
stressors formed in the source region and the drain region, respectively, wherein the metal silicide regions are formed in the stressors.
20. The semiconductor device as claimed in claim 11 , wherein the contact plugs electrically connect the metal silicide regions.