IP Library › Granted Patent US 9,236,263
Granted Patent B2
US 9,236,263 · App. 13/719,149 · Granted Jan 12, 2016

Method for fabricating semiconductor device including silicon-containing layer and metal-containing layer, and conductive structure of the same

Inventors: Kyong-Bong Rouh (Gyeonggi-do, KR); Shang-Koon Na (Gyeonggi-do, KR); Yong-Seok Eun (Gyeonggi-do, KR); Su-Ho Kim (Gyeonggi-do, KR); Tae-Han Kim (Gyeonggi-do, KR); Mi-Ri Lee (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
H01L21/283H01L21/28061H01L21/32136H01L21/32137H01L21/32139H01L21/76841H01L27/10885H01L27/10888H01L29/4941H01L27/10876
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Quick Facts
Patent No.
US 9,236,263
App. No.
13/719,149
Granted
Jan 12, 2016
Kind
B2
Abstract

A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer.

Claims (19)

1. A method for fabricating a semiconductor device, comprising:

forming a silicon-containing layer;

forming an undercut prevention layer over the silicon-containing layer;

forming a diffusion barrier layer over the undercut prevention layer;

forming a metal layer over the diffusion barrier layer;

etching the metal layer and the diffusion barrier layer; and

forming a conductive structure by etching the metal layer, the diffusion barrier layer, the undercut prevention layer and the silicon-containing layer,

wherein the metal layer includes tungsten silicide, tungsten nitride, tungsten or a combination thereof,

wherein the diffusion barrier layer includes tungsten silicide, tungsten nitride, tungsten silicon nitride or a combination thereof,

wherein the forming of the undercut prevention laver comprises injecting chemical species for controlling an etch rate,

wherein the injecting of the chemical species comprises implanting of carbon, and

wherein the conductive structure comprises a gate electrode or bit line.

2. The method of claim 1 , wherein the injecting of the chemical species comprises in-situ doping of carbon when the undercut prevention layer is formed.

3. The method of claim 1 , wherein a first polysilicon layer is formed as the silicon-containing layer, and a second polysilicon layer containing of carbon is formed as the undercut prevention layer.

4. The method of claim 3 , wherein the first and second polysilicon layers comprise a doped polysilicon layer with N-type or P-type impurities.

5. The method of claim 3 , wherein the first polysilicon layer is formed with an undoped polysilicon layer, and the second polysilicon layer is formed with a doped polysilicon layer with N-type or P-type impurities.

6. The method of claim 1 , wherein a polysilicon layer is formed as the silicon-containing layer, and the undercut prevention layer is formed by injecting of carbon into an upper part of the polysilicon layer.

7. The method of claim 1 , wherein the undercut prevention layer comprises a polysilicon layer doped with N-type or P-type impurities.

8. The method of claim 1 , wherein the metal-containing layer comprises a tungsten-based material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2012
From: ROUH, KYONG-BONG; NA, SHANG-KOON; EUN, YONG-SEOK; KIM, SU-HO; KIM, TAE-HAN; LEE, MI-RI
To: SK HYNIX INC.
Reel/Frame 029495/0618 →
Priority Claims (1)
KR 10-2012-0081835 · Jul 26, 2012 · national
Continuity (1)
Related Publication 20140030884A1 · Jan 30, 2014