System and method for internal AC coupling with active DC restore and adjustable high-pass filter for a PAM 2/4 receiver
A receiver termination circuit includes an internal AC coupling capacitor and an adjustable resistor forming an adjustable high-pass filter (HPF) at a receiver side of a transmission medium, and a digital-to-analog converter (DAC) coupled to the adjustable HPF, the DAC configured to provide a signal having a low-pass filter response to the adjustable HPF to provide a DC restore function.
1. A receiver termination circuit, comprising:
an internal AC coupling capacitor and an adjustable resistor forming an adjustable high-pass filter (HPF) at a receiver side of a transmission medium; and
a digital-to-analog converter (DAC) coupled to the adjustable HPF, the DAC configured to provide a signal having a low-pass filter response to the adjustable HPF to provide a DC restore function, wherein an RC characteristic of the adjustable HPF is adjustable by operation of the DAC and the adjustable resistor, and wherein the DC restore function provided by the DAC comprises digital feedback inserting receive data at frequencies in the range from DC to a high pass cutoff frequency set by an adjustable high-pass filter (HPF).
2. The circuit of claim 1 , wherein the DAC provides a signal having an adjustable amplitude to the adjustable HPF.
3. The circuit of claim 2 , wherein the DAC receives two logic level outputs as feedback signals.
4. The circuit of claim 3 , wherein at least one of the two logic level outputs comprise a complementary metal oxide semiconductor (CMOS) level logic output.
5. The circuit of claim 1 , wherein the low-pass filter response provided by the DAC and the high pass cutoff frequency are modulated together.
6. The circuit of claim 5 , wherein the DAC is controlled by an eight bit control word to operate in a PAM 2 modality.
7. The circuit of claim 5 , wherein the DAC is controlled by two eight bit control words to operate in a PAM 4 modality.
8. A method for operating a receiver circuit, comprising:
forming an adjustable-pass filter (HPF) at a receiver side of a transmission medium, the adjustable high-pass filter (HPF) comprising an internal AC coupling capacitor and an adjustable resistor that enables an RC characteristic of the adjustable HPF to be adjusted;
receiving a differential signal in the receiver; and
providing a signal having a low-pass filter response to the adjustable HPF to provide a DC restore function to the received signal, wherein the DC restore function comprises digital feedback inserting receive data at frequencies in the range from DC to a high pass cutoff frequency set by an adjustable high-pass filter (HPF).
9. The method of claim 8 , wherein a digital-to-analog converter (DAC) provides a signal having an adjustable amplitude to the adjustable HPF.
10. The method of claim 9 , wherein the DAC receives two logic level outputs as feedback signals.
11. The method of claim 10 , wherein at least one of the two logic level outputs comprise a complementary metal oxide semiconductor (CMOS) level logic output.
12. The method of claim 9 , further comprising modulating together the low-pass filter response provided by the DAC and the high pass cutoff frequency.
13. The method of claim 12 , further comprising controlling the adjustable amplitude of the DAC using an eight bit control word to operate in a PAM 2 modality.
14. The method of claim 12 , further comprising controlling the adjustable amplitude of the DAC using two eight bit control words to operate in a PAM 4 modality.
15. A receiver for a serializer/deserializer (SERDES), comprising:
an internal AC coupling capacitor and an adjustable resistor forming an adjustable high-pass filter (HPF) at a receiver side of a transmission medium; and
a digital-to-analog converter (DAC) coupled to the adjustable HPF, the DAC configured to provide a signal having a low-pass filter response to the adjustable HPF to provide a DC restore function, wherein an RC characteristic of the adjustable HPF is adjustable by operation of the DAC and the adjustable resistor, and wherein the DC restore function provided by the DAC comprises digital feedback inserting receive data at frequencies in the range from DC to a high pass cutoff frequency set by an adjustable high-pass filter (HPF).
16. The receiver of claim 15 , wherein the DAC provides a signal having an adjustable amplitude to the adjustable HPF.
17. The receiver of claim 16 , wherein the DAC receives two logic level outputs as feedback signals.
18. The receiver of claim 17 , wherein at least one of the two logic level outputs comprise a complementary metal oxide semiconductor (CMOS) level logic output.
19. The receiver of claim 15 , wherein the low-pass filter response provided by the DAC and the high pass cutoff frequency are modulated together.
20. The receiver of claim 19 , wherein the DAC is controlled by an eight bit control word to operate in a PAM 2 modality.
21. The receiver of claim 19 , wherein the DAC is controlled by two eight bit control words to operate in a PAM 4 modality.