IP Library Granted Patent US 9,239,609
Granted Patent B2
US 9,239,609 · App. 14/057,277 · Granted Jan 19, 2016

Method for reducing power consumption in electronic apparatus

Inventor: Cheng-Ming Huang (New Taipei, TW)
Assignee: VIA TECHNOLOGIES, INC.
G06F1/324G06F1/3212
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Quick Facts
Patent No.
US 9,239,609
App. No.
14/057,277
Granted
Jan 19, 2016
Kind
B2
Abstract

An electronic apparatus is provided. The electronic apparatus includes a serial advanced technology attachment (SATA) physical layer, a clock generator and a control unit. The SATA physical layer is configured to provide connection with an SATA device and perform data transmission with the SATA device is performed at a first clock frequency. The clock generator is configured to provide a clock signal having the first clock frequency to the SATA physical layer. When at least one specific event is detected by the control unit, the control unit controls the clock generator to provide the clock signal having a second clock frequency to the SATA physical layer, so that the SATA physical layer performs data transmission with the SATA device at the second clock frequency. The second clock frequency is lower than the first clock frequency.

Claims (32)

1. An electronic apparatus, comprising

a serial advanced technology attachment (SATA) physical layer, configured to provide connection with an SATA device for building a transmission link, wherein the SATA physical layer performs data transmission with the SATA device at a first clock frequency;

a clock generator, configured to provide a clock signal having the first clock frequency to the SATA physical layer; and

a control unit, wherein after the transmission link is built between the SATA device and the electronic apparatus, when at least one specific event is detected by the control unit, the control unit controls the clock generator to dynamically provide the clock signal having a second clock frequency to the SATA physical layer, so that the SATA physical layer performs the data transmission with the SATA device at the second clock frequency, wherein the second clock frequency is lower than the first clock frequency.

2. The electronic apparatus as claimed in claim 1 , wherein the at least one specific event indicates that a remaining battery capacity of a power supply of the electronic apparatus is lower than a predetermined threshold value.

3. The electronic apparatus as claimed in claim 1 , wherein the at least one specific event indicates that an idle count within a predetermined period is larger than a predetermined threshold value.

4. The electronic apparatus as claimed in claim 1 , wherein the at least one specific event indicates that an amount of data transmitted by the control unit is smaller than a predetermined value.

5. The electronic apparatus as claimed in claim 1 , wherein when the at least one specific event is detected by the control unit, the control unit further controls the clock generator to stop providing the clock signal having the first clock frequency to terminate the transmission link between the electronic apparatus and the SATA device.

6. The electronic apparatus as claimed in claim 5 , wherein the control unit further controls the clock generator to provide the clock signal having the second clock frequency, so that the control unit responds to a second alignment signal corresponding to the second clock frequency from the SATA device to rebuild the transmission link.

7. The electronic apparatus as claimed in claim 6 , wherein when the SATA device transmits a first alignment signal corresponding to the first clock frequency to the electronic apparatus, the control unit does not respond to the first alignment signal from the SATA device, and

wherein when the SATA device does not receive a response to the first alignment signal, the SATA device generates the second alignment signal corresponding to the second clock frequency, and the control unit responds to the second alignment signal to rebuilt the transmission link.

8. The electronic apparatus as claimed in claim 1 , wherein the control unit further comprises:

a first register, having a first value configured to control activating and deactivating of the clock generator; and

a second register, having a second value configured to control a clock frequency of the clock signal generated by the clock generator.

9. A method for reducing power consumption of an electronic apparatus, wherein the electronic apparatus comprises an SATA physical layer and a clock generator, the method comprising:

utilizing the clock generator to provide a clock signal having a first clock frequency to the SATA physical layer;

utilizing the SATA physical layer to connect to an SATA device for building a transmission link, wherein the SATA physical layer performs data transmission with the SATA device at a first clock frequency; and

when at least one specific event is detected after the transmission link is built between the SATA device and the electronic apparatus, the clock generator dynamically provides the clock signal having a second clock frequency to the SATA physical layer, so that the SATA physical layer performs the data transmission with the SATA device at the second clock frequency,

wherein the second clock frequency is lower than the first clock frequency.

10. The method as claimed in claim 9 , wherein the at least one specific event indicates that a remaining battery capacity of a power supply of the electronic apparatus is lower than a predetermined threshold value.

11. The method as claimed in claim 9 , wherein the at least one specific event indicates that an idle count within a predetermined period is larger than a predetermined threshold value.

12. The method as claimed in claim 9 , wherein the at least one specific event indicates that an amount of data transmitted by the control unit is smaller than a predetermined value.

13. The method as claimed in claim 9 , further comprising:

controlling the clock generator to stop providing the clock signal having the first clock frequency to terminate the transmission link between the electronic apparatus and the SATA device when the at least one specific event is detected.

14. The method as claimed in claim 13 , further comprising:

controlling the clock generator to provide the clock signal having the second clock frequency to respond to a second alignment signal corresponding to the second clock frequency from the SATA device to rebuild the transmission link.

15. The method as claimed in claim 14 , wherein the step of rebuilding the transmission link further comprises:

ignoring a first alignment signal corresponding to the first clock frequency from the SATA device; and

when the SATA device does not receive a response to the first alignment signal and generates a second alignment signal corresponding to the second clock frequency, responding to the second alignment signal to rebuild the transmission link.

16. The method as claimed in claim 9 , further comprising:

utilizing a first value of a first register of the electronic apparatus to control activating and deactivating of the clock generator; and

utilizing a second value of a second register of the electronic apparatus to control a clock frequency of the clock signal generated by the clock generator.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2019
From: VIA TECHNOLOGIES, INC.
To: VIA LABS, INC.
Reel/Frame 051075/0258 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2013
From: HUANG, CHENG-MING
To: VIA TECHNOLOGIES, INC.
Reel/Frame 031433/0680 →
Priority Claims (1)
TW 102131491 A · Sep 2, 2013 · national
Continuity (1)
Related Publication 20150067367A1 · Mar 5, 2015