IP Library Granted Patent US 9,240,323
Granted Patent B2
US 9,240,323 · App. 13/788,599 · Granted Jan 19, 2016

Methods of forming semiconductor devices with metal silicide using pre-amorphization implants

Inventors: Chung-Hwan Shin (Seoul, KR); Sang-Bom Kang (Seoul, KR); Dae-Yong Kim (Yongin-si, KR); Jeong-Ik Kim (Seoul, KR); Chul-Sung Kim (Seongnam-si, KR); Je-Hyung Ryu (Suwon-si, KR); Sang-Woo Lee (Seoul, KR); Hyo-Seok Choi (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L21/28H01L21/26506H01L21/28518H01L21/76814H01L23/485H01L29/165H01L29/66636H01L29/78H01L2924/0002
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Quick Facts
Patent No.
US 9,240,323
App. No.
13/788,599
Granted
Jan 19, 2016
Kind
B2
Abstract

A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

Claims (23)

1. A method of forming a semiconductor device comprising:

forming an opening that exposes a surface of an elevated source/drain region; and

forming a metal-silicide in the elevated source/drain region to include a silicide lower profile that is remote from the surface, the silicide lower profile having a curved cross-section, wherein the metal-silicide includes an upper recess having a bottom and a sidewall, wherein the bottom is separated from a bottom of the silicide lower profile by a distance that is greater than a distance by which the sidewall of the recess is separated from a sidewall of the silicide lower profile, wherein the sidewall of the recess is coplanar with a sidewall of the opening, wherein a diameter of a bottom of the opening is 20 nm or less.

2. The method of claim 1 further comprising before forming a metal-silicide, performing a pre-amorphization implant (PAI) into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region, and

wherein forming a metal-silicide comprises forming a metal-silicide from a metal and the amorphized portion.

3. The method of claim 2 wherein performing the PAI comprises forming the amorphized portion to include a PAI lower profile that is remote from the surface, the PAI lower profile having a curved cross-section.

4. The method of claim 3 wherein a central portion of the curved cross-section is curved.

5. The method of claim 3 wherein performing the PAI comprises implanting Xe into the elevated source/drain region to form the amorphized portion including the PAI lower profile, the amorphized portion having a total thickness of at least 100 Angstroms.

6. The method of claim 3 wherein performing the PAI comprises implanting Si into the elevated source/drain region to form the amorphized portion including the PAI lower profile, the amorphized portion having a total thickness of at least 100 Angstroms.

7. The method of claim 1 further comprising applying an RF etch to the opening before forming a metal-silicide.

8. The method of claim 7 wherein applying an RF etch to the opening comprises applying an RF etch to the sidewall of the opening to re-deposit material from an upper portion of the sidewall to a lower portion of the sidewall to form an increased curvature surface at the bottom of the opening at the elevated source/drain region.

9. The method of claim 1 wherein forming the metal-silicide comprises forming the silicide lower profile at a level that is equal to or higher than a gate oxide layer included in a gate structure that is directly adjacent to the elevated source/drain region.

10. The method of claim 1 wherein forming the metal-silicide comprises forming the silicide lower profile at a level that is elevated above an uppermost surface of a channel region associated with at least one directly adjacent gate structure.

11. The method of claim 1 wherein a depth of the silicide lower profile in the elevated source/drain region is more than one half of a total thickness of the elevated source/drain region.

12. A method of forming a semiconductor device comprising:

performing a first etch to form an opening that exposes a surface of an elevated source/drain region;

performing an RF etch in the opening to re-deposit material from an upper sidewall of the opening to a lower sidewall of the opening to reduce a critical dimension of the opening at the surface of the elevated source/drain region and to change a shape of the lower sidewall to provide an increased curvature surface at the elevated source/drain region;

performing a pre-amorphization implant (PAI) into the increased curvature surface to form an amorphized portion of the elevated source/drain region; and

forming a metal-silicide in the elevated source/drain region from a metal and the amorphized portion of the elevated source/drain region.

13. The method of claim 12 wherein forming a metal-silicide comprises forming the metal-silicide to include a silicide lower profile that is remote from the surface, the silicide lower profile having a curved cross-section.

14. The method of claim 13 wherein the metal-silicide includes an upper recess having a bottom and a sidewall, wherein the bottom of the upper recess is separated from a bottom of the silicide lower profile by a distance that is greater than a distance by which the sidewall of the recess is separated from a sidewall of the silicide lower profile, wherein the sidewall of the upper recess is coplanar with the lower sidewall of the opening.

15. The method of claim 12 wherein performing the RF etch comprises RF etching the opening using an inert ion.

16. The method of claim 12 wherein the re-deposited material remains on the lower sidewall of the opening during the pre-amorphization implant.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE DOC DATE "02/13/2013" FOR ASSIGNOR LEE, SANG-WOO PREVIOUSLY RECORDED ON REEL 029943 FRAME 0690. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT DOC DATE IS --02/12/2013-- FOR ASSIGNOR LEE, SANG-WOO. Recorded Mar 28, 2013
From: SHIN, CHUNG-HWAN; KANG, SANG-BOM; KIM, DAE-YONG; KIM, JEONG-IK; KIM, CHUL-SUNG; RYU, JE-HYUNG; LEE, SANG-WOO; CHOI, HYO-SEOK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 030111/0553 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2013
From: SHIN, CHUNG-HWAN; KANG, SANG-BOM; KIM, DAE-YONG; KIM, JEONG-IK; KIM, CHUL-SUNG; RYU, JE-HYUNG; LEE, SANG-WOO; CHOI, HYO-SEOK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 029943/0690 →
Priority Claims (1)
KR 10-2012-0055543 · May 24, 2012 · national
Continuity (1)
Related Publication 20130316535A1 · Nov 28, 2013