IP Library Granted Patent US 9,240,461
Granted Patent B2
US 9,240,461 · App. 13/932,047 · Granted Jan 19, 2016

Method for fabricating semiconductor device

Inventors: Seok-Hoon Kim (Hwaseong-si, KR); Dong-Chan Suh (Seoul, KR); Byeong-Chan Lee (Yongin-s, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L29/6656H01L21/764H01L21/7682H01L29/165H01L29/6653H01L29/66545H01L29/66636H01L29/7848H01L29/4966H01L29/517
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,240,461
App. No.
13/932,047
Granted
Jan 19, 2016
Kind
B2
Abstract

A method for fabricating a semiconductor device comprises forming a dummy gate pattern and a spacer that is arranged on a sidewall of the dummy gate pattern on a substrate, forming an air gap on both sides of the dummy gate pattern by removing the spacer, exposing the substrate by removing the dummy gate pattern, and sequentially forming a gate insulating film including a high-k insulating film and a metal gate electrode on the exposed substrate.

Claims (43)

1. A method for fabricating a semiconductor device comprising:

forming a dummy gate pattern on a substrate;

forming a spacer on a sidewall of the dummy gate pattern and on the substrate;

forming a trench by etching the substrate at a side surface of the spacer;

forming a semiconductor pattern in the trench where the semiconductor pattern protrudes from the trench above a top surface of the substrate;

forming a first recess by removing at least part of the spacer;

forming an air gap on both sides of the dummy gate pattern by forming a blocking film that covers the first recess and the dummy gate pattern;

exposing the substrate by removing the dummy gate pattern; and

sequentially forming a gate insulating film including a high-k insulating film and a metal gate electrode on the exposed substrate.

2. The method for fabricating the semiconductor device of claim 1 , wherein forming the first recess comprises:

forming an interlayer insulating film that at least partially covers a sidewall of the spacer and exposes a top surface of the spacer; and

forming the first recess in the interlayer insulating film by removing at least part of the spacer.

3. The method for fabricating the semiconductor device of claim 2 , further comprising conformally forming a liner within the first recess.

4. The method for fabricating the semiconductor device of claim 2 , wherein removing at least part of the spacer comprises leaving a lower part of the spacer on the substrate.

5. The method for fabricating the semiconductor device of claim 1 , wherein a part of the blocking film fills up an upper portion of the first recess while leaving the air gap in a lower portion of the first recess.

6. The method for fabricating the semiconductor device of claim 5 , wherein removing the dummy gate pattern comprises:

exposing the dummy gate pattern by smoothing the blocking film; and

forming a trench that exposes the substrate in the interlayer insulating film by etching the exposed dummy gate pattern.

7. The method for fabricating the semiconductor device of claim 1 , further comprising forming an air gap spacer on the sidewall of the dummy gate pattern.

8. The method for fabricating the semiconductor device of claim 7 , wherein forming the air gap spacer comprises:

forming a filler that fills up the first recess; and

forming a second recess by removing a part of the filler.

9. The method for fabricating the semiconductor device of claim 8 , further comprising removing the filler after forming the air gap spacer.

10. A method of fabricating a semiconductor device, the method comprising:

forming a first gate electrode and a second gate electrode on a substrate;

forming an interlayer pattern between the first and second gate electrodes;

conformally forming a first layer on the first and second gate electrodes and on the interlayer pattern; and then

forming a blocking film on the first and second gate electrodes and on the interlayer pattern,

wherein the blocking film only partially fills a first air gap between the first gate electrode and the interlayer pattern, and only partially fills a second air gap between the second gate electrode and the interlayer pattern.

11. The method of fabricating the semiconductor device of claim 10 , the method further comprising the following steps prior to formation of the first layer:

forming a first spacer on a first sidewall of the first gate electrode and forming a second spacer on a second sidewall of the second gate electrode; and

removing the first and second spacer to form the first and second air gaps.

12. The method of fabricating the semiconductor device of claim 11 , wherein the first and second gate electrodes comprise first and second dummy gate electrodes, the interlayer pattern comprises a patterned interlayer insulating film, and the first layer comprises a liner layer the method further comprising:

removing the first and second dummy gate electrodes; and

forming first and second metal gate electrodes in place of the first and second dummy gate electrodes.

13. The method of fabricating the semiconductor device of claim 11 , the method further comprising:

forming a trench by etching the substrate between the first and second spacers, and

forming a semiconductor pattern in the trench, the semiconductor pattern protruding above a top surface of the substrate.

14. The method of fabricating the semiconductor device of claim 10 , wherein the first and second gate electrodes comprise first and second dummy gate electrodes, the interlayer pattern comprises a patterned interlayer insulating film, and the first layer comprises a liner the method further comprising the following steps after forming the liner but prior to forming the blocking film:

forming a filler on the liner that fills up the first and second air gaps;

forming a first recess and a second recess by removing respective first and second portions of filler;

forming a first air gap spacer on a sidewall of the first recess and forming a second air gap spacer on a sidewall of the second recess; and

removing the filler after forming the first and second air gap spacers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2013
From: KIM, SEOK-HOON; SUH, DONG-CHAN; LEE, BYEONG-CHAN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 030717/0106 →
Priority Claims (1)
KR 10-2012-0079355 · Jul 20, 2012 · national
Continuity (1)
Related Publication 20140024192A1 · Jan 23, 2014