Enhanced GaN transistor and the forming method thereof
An enhanced GaN transistor is provided. The structure comprises a substrate, a heterostructure, a p-element epitaxy growth layer, a drain ohmic contact and a source ohmic contact disposed on the heterostructure and on two sides of the p-element epitaxy growth layer, a gate structure disposed on the p-element epitaxy growth layer, and is separated from the drain ohmic contact and the source ohmic contact, a surface passivation layer covered the drain ohmic contact, source ohmic contact, and p-element epitaxy growth layer, and covered portion of the gate structure.
1. An enhanced GaN transistor by having an In x Al 1-x N/AlN heterostructure to raise an output current and having a p-In x Al 1-x N layer to raise a threshold voltage, comprising:
a substrate, wherein the substrate is selected from the group consisting of silicon carbide (SiC) and silicon;
a In x Al 1-x N/AlN heterostructure being disposed on the substrate in order to raise an output current;
a p-In x Al 1-x N layer being disposed on the In x Al 1-x N/AlN heterostructure to form a P-N junction in order to raise a threshold voltage;
a drain ohmic contact is disposed on the In x Al 1-x N/AlN heterostructure, and a source ohmic contact is disposed on the In x Al 1-x N/AlN heterostructure, formed on two sides of the p-In x Al 1-x N layer;
a gate structure being disposed on the p-In x Al 1-x N layer and separated from the drain ohmic contact and the source ohmic contact; and
a surface passivation layer covers the drain ohmic contact, the source ohmic contact, the p-In x Al 1-x N layer and a portion of the gate structure, wherein the surface passivation layer comprises silicon nitride (SiN).
2. A forming method for the enhanced GaN transistor by having an In x Al 1-x N/AlN heterostructure to raise an output current and having a p-In x Al 1-x N layer to raise a threshold voltage, comprising;
providing a substrate, wherein the substrate is selected from the group consisting of silicon carbide (SiC) and silicon;
forming a In x Al 1-x N/AlN heterostructure on the substrate in order to raise an output current;
forming a p-In x Al 1-x N layer on the In x Al 1-x N/AlN heterostructure to form a P-N junction in order to raise a threshold voltage;
forming a first photoresist layer on the p-In x Al 1-x N layer and forming a drain region and a source region on two sides of the p-In x Al 1-x N layer;
etching to remove a portion of the p-In x Al 1-x N depositing a first metal layer on two sides of the p-In x Al 1-x N growth layer to form a drain ohmic contact and a source ohmic contact;
forming a second photoresist layer on the p-In x Al 1-x N layer, and defining a gate region on the p-In x Al 1-x N layer;
depositing a second metal layer on the p-In x Al 1-x N layer;
etching to remove a portion of the second metal layer by using an inductively coupled plasma (ICP) to form a gate structure on the p-In x Al 1-x N layer, separating the gate structure from the drain ohmic contact and the source ohmic contact; and
depositing a surface passivation layer to cover the drain ohmic contact, the source ohmic contact, the p-In x Al 1-x N layer and a portion of the gate structure.
3. The method according to claim 1 , wherein the plasma enhanced chemical vapor deposition (PECVD) is used to deposit the surface passivation layer.
4. The method according to claim 1 , wherein the surface passivation layer comprises silicon nitride (SiN).