Clock synchronization circuit and semiconductor memory device including clock synchronization circuit
A clock synchronization circuit includes a delay-locked loop (DLL) and a delay-locked control unit. The DLL is configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal. The delay-locked control unit configured to detect the locked state of the DLL, and to control the DLL based on the determined locked state.
1. A clock synchronization circuit comprising:
a delay-locked loop (DLL) configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal; and
a delay-locked control unit configured to detect the locked state of the DLL, and to generate a delay-locked disable signal when the locked state is detected as being maintained for a predetermined period of time, wherein the DLL is responsive to the delay-locked disable signal to terminate the delay-locking operation in which the delay time is adjusted,
wherein the delay-locked control unit is configured to generate the delay-locked disable signal responsive to an obtained court value of the input clock signal,
wherein the delay-locked control unit comprises:
a locked detector that determines whether the DLL is in the locked state, and outputs a delay-locked signal; and
a counter that counts a time in which the locked state is maintained based on the delay-locked signal to obtain the count value, and to output the delay-locked disable signal when the count value is equal to or greater than a predetermined value, and
wherein the counter counts the input clock signal when the delay-locked signal has first logic level, and the counter is rest when the delay-locked signal has a second logic level.
2. The clock synchronization circuit of claim 1 , wherein when the delay-locking operation is terminated, the delay-locked control unit terminates the detected locked state of the DLL.
3. The clock synchronization circuit of claim 2 , wherein the predetermined period of time is set according to an external setting signal.
4. The clock synchronization circuit of claim 2 , wherein the predetermined period of time is set according to a phase difference between the input clock signal and the output clock signal in the locked state.
5. The clock synchronization circuit of claim 1 , wherein the DLL comprises:
a phase detector configured to generate an up-down signal based on a phase difference between the input clock signal and the output clock signal;
a delay controller configured to output a delay control signal for adjusting the delay time in response to the up-down signal; and
a delay line configured to delay the input clock signal according to the delay control signal.
6. The clock synchronization circuit of claim 5 , wherein the locked detector is configured to receive the up-down signal, and determine whether the DLL is in the locked state based on a number of repetitions of an up state or a down state of the up-down signal.
7. The clock synchronization circuit of claim 5 , wherein the locked detector is configured to determine whether the DLL is locked based on the phase difference between the input clock signal and the output clock signal.
8. The clock synchronization circuit of claim 5 , wherein the locked detector is configured to determine whether the DLL is locked based on a change in value of the delay control signal.
9. The clock synchronization circuit of claim 1 , wherein the clock synchronization circuit is applied to a semiconductor device that inputs or outputs data in synchronization with an external device,
wherein when an operational state of the semiconductor device is changed, the delay-locking operation of the DLL is performed.
10. A clock synchronization circuit comprising:
a delay-locked loop (DLL) configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal; and
a delay-locked control unit configured to detect the locked state of the DLL, and to generate a delay-locked disable signal when the locked state is detected as being maintained for a predetermined period of time, wherein the DLL is responsive to the delay-locked disable signal to terminate the delay-locking operation in which the delay time is adjusted,
wherein the delay-locked control unit is configured to generate the delay-locked disable signal responsive to an obtained count value of the input clock signal,
wherein the delay-locked control unit comprises:
a locked detector that determines whether the DLL is in the locked state, and outputs a delay-locked signal; and
a counter that counts a time in which the locked state is maintained based on the delay-locked signal to obtain the count value, and to output the delay-locked disable signal when the count value is equal to or greater than a predetermined value,
wherein the DLL comprises:
a phase detector configured to generate an up-down signal based on a phase difference between the input clock signal and the output clock signal;
a delay controller configured to output a delay control signal for adjusting the delay time in response to the up-down signal;
a delay line configured to delay the input clock signal according to the delay control signal;
a first clock buffer that buffers a received clock signal, and generates a first clock signal that is applied as a reference clock signal of the delay controller and as the input clock signal to the counter;
a second clock buffer that buffers the received clock signal, and generates the input clock signal that is applied to the delay line;
a third clock buffer that buffers an output of the delay line, and generates the output clock signal that is applied to the phase detector; and
a fourth clock buffer that buffers the output of the delay line, and generates another output clock signal that has a same phase as the output clock signal that is applied to the phase detector, and
wherein operations of the first clock buffer and the third clock buffer are stopped in response to the delay-locked disable signal.
11. A clock synchronization circuit comprising:
a delay-locked loop (DLL) configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal; and
a delay-locked control unit configured to detect the locked state of the DLL, and to generate a delay-locked disable signal when the locked state is detected as being maintained for a predetermined period of time, wherein the DLL is responsive to the delay-locked disable signal to terminate the delay-locking operation in which the delay time is adjusted,
wherein the delay-locked control unit is configured to generate the delay-locked disable signal responsive to an obtained count value of the input clock signal,
wherein the delay-locked control unit comprises:
a locked detector that determines whether the DLL is in the locked state, and outputs a delay-locked signal; and
a counter that counts a time in which the locked state is maintained based on the delay-locked signal to obtain the count value, and to output the delay-locked disable signal when the count value is equal to or greater than a predetermined value,
wherein the DLL comprises:
a phase detector configured to generate an up-down signal based on a phase difference between the input clock signal and the output clock signal;
a delay controller configured to output a delay control signal for adjusting the delay time in response to the up-down signal;
a delay line configured to delay the input clock signal according to the delay control signal;
a first clock buffer that buffers an output of the delay line, and generates a first clock signal that is applied as a reference clock signal of the delay controller and as the input clock signal to the counter, and is applied to the phase detector as the output clock signal; and
a second clock buffer that buffers the output of the delay line, and generates a second clock signal that has a same phase as the output clock signal that is applied to the phase detector, and
wherein an operation of the first clock buffer is stopped in response to the delay-locked disable signal.