Chip with programmable shelf life
A method includes forming a first interconnect structure and a second interconnect structure each located within an interlevel dielectric (ILD). A first top metal layer and a second top metal layer are formed disposed on and in direct electrical connection with the first interconnect. Similarly, a third top metal layer and a fourth top metal layer are formed disposed on and in direct electrical connection with the second interconnect. A silicon layer is deposited above the first, second, third and fourth top metal layers in direct contact with the first and fourth top metal layers and separated from each of the second and third top metal layers by a barrier layer. The silicon layer is exposed to an oxygen-containing environment to form a silicon dioxide layer.
1. A method comprising:
forming a first interconnect structure and a second interconnect structure each located within an interlevel dielectric (ILD);
forming a first top metal layer and a second top metal layer disposed on and in direct electrical connection with the first interconnect;
forming a third top metal layer and a fourth top metal layer disposed on and in direct electrical connection with the second interconnect;
forming a silicon layer above the first, second, third and fourth top metal layers, the silicon layer is in direct contact with the first and fourth top metal layers;
forming a barrier layer separating the silicon layer from each of the second and third top metal layers; and
exposing the silicon layer to an oxygen-containing environment to form a silicon dioxide layer.
2. The method of claim 1 , wherein the silicon dioxide layer acts as an insulator material creating a high resistance connection between the third and fourth top metal layers that damages the electrical connection between the third and fourth top metal layers.
3. The method of claim 1 , wherein the first, second, third and fourth top metal layers comprise a copper-rich material.
4. The method of claim 3 , wherein copper atoms from the first and fourth top metal layers diffuse to an interface between the silicon layer and the silicon dioxide layer to catalyze an oxidation of the silicon layer.
5. The method of claim 1 , wherein a length of the silicon layer determines a time for the silicon layer to be oxidized and form the silicon dioxide layer.
6. The method of claim 1 , further comprising:
entering a code to bypass the damaged electrical connection between the third and fourth top metal layers to reestablish current flow.
7. A method comprising:
forming a plurality of top metal layers in an interlevel dielectric (ILD), the plurality of top metal layers are electrically connected to one or more interconnect structures of an IC chip;
forming a barrier layer directly above two adjacent top metal layers, the two adjacent top metal layers being located between two outer top metal layers;
forming a silicon layer above the two adjacent top metal layers and the two outer top metal layers, the silicon layer being directly on top of the outer top metal layers;
wherein the silicon layer is separated from the two adjacent top metal layers by the barrier layer forming a sensing circuit;
exposing the IC chip to an oxygen-containing environment to oxidize the silicon layer and form a silicon dioxide layer, wherein oxidation of the silicon layer damages the sensing circuit and makes the IC chip inoperable.
8. The method of claim 7 , wherein the top metal layers comprise a copper-rich material.
9. The method of claim 8 , wherein copper atoms from the outer top metal layers diffuse to an interface between the silicon layer and the silicon dioxide layer to catalyze the oxidation of the silicon layer.
10. The method of claim 7 , wherein exposing the IC chip to the oxygen-containing environment to oxidize the silicon layer and form the silicon dioxide layer comprises the silicon dioxide layer acting as an insulator material creating a high resistance connection between the two adjacent top metal layers and the silicon dioxide layer that halts current flow disabling the sensing circuit and forming an electrical open that damages the IC chip.
11. The method of claim 7 , wherein a length of the silicon layer determines a time for the silicon layer to be oxidized and form the silicon dioxide layer.
12. The method of claim 11 , wherein the time for the silicon layer to be oxidized corresponds to a shelf life of the IC chip.
13. The method of claim 7 , wherein the oxygen-containing environment comprises an oxygen-containing fluid such as air.
14. The method of claim 7 , wherein the oxidation of the silicon layer occurs at ambient conditions of pressure and temperature.
15. The method of claim 1 , further comprising:
reprogramming the IC chip to function without the damaged sensing circuit to regain operability.
16. The method of claim 15 , wherein reprogramming the IC chip comprises applying a suitable code to bypass the damaged sensing circuit and make the IC chip to work again.