Vertically stackable dies having chip identifier structures
A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact.
1. A computer-readable storage device storing instructions executable by a computer, the instructions comprising:
instructions that are executable by the computer to initiate forming a first die, wherein the first die comprises:
a first through silicon via to communicate a chip identifier and other data; and
a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact.
2. The computer-readable storage device of claim 1 , further comprising instructions that are executable by the computer to initiate coupling each external electrical contact to a voltage source or to ground.
3. The computer-readable storage device of claim 1 , wherein each of the at least two through silicon vias has a pad that is configured to be coupled to an adjacent through silicon via and the first through silicon via is coupled to its own pad.
4. The computer-readable storage device of claim 1 , further comprising instructions that are executable by the computer to initiate forming a second die, wherein the first die and the second die comprise structurally identical circuitry.
5. The computer-readable storage device of claim 4 , further comprising instructions that are executable by the computer to initiate stacking the second die above the first die.
6. The computer-readable storage device of claim 1 , integrated in at least one semiconductor die.
7. The computer-readable storage device of claim 1 , wherein the computer-readable storage device is integrated within a computer.
8. A method comprising:
receiving a chip identifier signal at a first die, wherein the chip identifier signal is received at the first die via multiple through silicon vias (TSVs) of the first die;
receiving, at the first die, a chip selection signal different than the chip identifier signal; and
determining, based on the chip identifier signal, whether the first die is a particular die that is indicated by the chip selection signal.
9. The method of claim 8 , wherein: a first TSV of a chip identifier structure of the first die has a pad that is coupled to a second TSV of the chip identifier structure of the first die, the second TSV adjacent to the first TSV; and wherein at least a portion of the chip identifier signal is received at the pad, from a third TSV of a second die, and conveyed to the second TSV.
10. The method of claim 9 , wherein the pad is located below the first TSV.
11. The method of claim 9 , wherein the pad is located between the first TSV and the third TSV.
12. The method of claim 8 , further comprising a second die stacked above the first die, wherein the first die and the second die comprise structurally identical circuitry.
13. The method of claim 8 , wherein determining whether the first die is the particular die is performed at chip identification decoding logic integrated in a semiconductor die.
14. The method of claim 8 , wherein the chip selection signal is received via a first TSV at the first die, and wherein the first TSV is different than the multiple TSVs.
15. The method of claim 8 , wherein determining whether the first die is the particular die is performed at chip identifier selection logic coupled to the multiple TSVs, and wherein the chip identifier selection logic receives a signal from a host device that corresponds to the chip selection signal.
16. The method of claim 15 , wherein the chip identifier selection logic detects a voltage source or ground at each of the multiple TSVs.
17. A method comprising:
a step for receiving a chip identifier signal at a first die, wherein the chip identifier signal is received at the first die via multiple through silicon vias (TSVs) of the first die;
a step for receiving, at the first die, a chip selection signal different than the chip identifier signal; and
a step for determining, based on the chip identifier signal, whether the first die is a particular die that is indicated by the chip selection signal, wherein the chip selection signal is received via a first TSV at the first die, the first TSV different than the multiple TSVs, and wherein the step for determining is performed at chip identification decoding logic integrated in a semiconductor die.
18. A method comprising:
receiving a data file comprising design information corresponding to a semiconductor device; and
fabricating the semiconductor device according to the design information, wherein the semiconductor device comprises:
a first die comprising:
a first through silicon via (TSV) to communicate a chip selection signal; and
multiple TSVs to communicate a chip identifier signal different than the chip selection signal, the multiple TSVs hard wired to a set of external electrical contacts.
19. The method of claim 18 , wherein the multiple TSVs are different than the first TSV and correspond to a chip identifier structure of the first die, wherein the data file has a GD SII format.
20. The method of claim 18 , wherein the multiple TSVs are different than the first TSV and correspond to a chip identifier structure of the first die, and wherein the data file has a GERBER format.
21. A method comprising:
receiving a data file comprising design information corresponding to a semiconductor device; and
fabricating the semiconductor device according to the design information, wherein the semiconductor device comprises:
a first die comprising:
a first set of through silicon vias (TSVs) hard wired to a set of external electrical contacts to communicate a chip identifier signal; and
a first TSV to communicate a chip selection signal different than the chip identifier signal; and
a second die comprising a second set of TSVs hard wired to corresponding TSVs of the first set of TSVs.
22. The method of claim 21 , wherein the first set of TSVs is different than the first TSV, and wherein the data file has a GDSII format.
23. The method of claim 21 , wherein the first set of TSVs is different than the first TSV, and wherein the data file has a GERBER format.
24. The method of claim 21 , wherein the first die comprises a first chip identifier structure corresponding to the first set of TSVs and the second die comprises a second chip identifier structure corresponding to the second set of TSVs.
25. A method comprising:
receiving, at a first through silicon via (TSV) of a first die, at least a portion of a chip identifier signal from a second TSV of a second die; and
determining, based on the at least a portion of the chip identifier signal, whether the first die is a particular die that is indicated by a chip selection signal.
26. The method of claim 25 , wherein a third TSV of a chip identifier structure of the first die corresponds to a pad that is coupled to the first TSV, the first TSV adjacent to the third TSV, and wherein the at least a portion of the chip identifier signal is received at the pad from the second TSV and conveyed to the first TSV.
27. The method of claim 26 , wherein the pad is located between the third TSV and the second TSV.
28. The method of claim 25 , wherein the chip selection signal is received via a third TSV at the first die, the third TSV different than the second TSV.
29. The method of claim 25 , the first die and the second die comprising structurally identical circuitry.
30. The method of claim 25 , wherein determining whether the first die is the particular die is performed at chip identifier selection logic coupled to the first die, the chip identifier selection logic coupled to receive a signal corresponding to the chip select signal from a host device.