Vertical double-diffusion MOS and manufacturing technique for the same

1. A method of making a vertical double-diffusion MOS (VDMOS) transistor, the method comprising:

a) etching an isolated oxide layer formed on a surface of an epitaxial structure to define an active region of said VDMOS transistor;

b) injecting a first dopant into said active region, and diffusing said first dopant to form a doping region, wherein said doping region comprises a body region for said VDMOS transistor;

c) after said body region is formed, forming a gate oxide layer on a surface of said active region;

d) depositing polysilicon on said gate oxide layer, and etching said polysilicon to form a gate;

e) injecting a second dopant at an end of said gate to form a source in said body region, wherein said first and second dopants have opposite types;

f) forming a contact hole adjacent to said gate, and injecting a third dopant into said contact hole, wherein said first and third dopants have a same type;

g) depositing and etching aluminum on a chip surface; and

h) coating said aluminum and said chip surface with a passivation layer.

2. The method of claim 1 , wherein said forming said active region and said gate comprise using a same mask.

3. The method of claim 1 , further comprising performing JFET injection and diffusion at said active region.

4. The method of claim 1 , further comprising performing depleted channel injection to said active region to form a depletion layer, wherein said depletion layer and said first dopant have opposite types.

5. The method of claim 4 , further comprising:

a) etching said gate oxide layer; and

b) forming a new gate oxide layer at said active region.

6. The method of claim 1 , wherein said body region comprises a P-body region.

7. The method of claim 1 , wherein said body region comprises an N-body region.

8. The method of claim 1 , wherein said epitaxial structure is on a substrate.

9. A vertical double-diffusion MOS (VDMOS) transistor, comprising:

a) an isolated field oxide layer on an epitaxial structure, wherein said isolated field oxide layer covers surface areas outside of an active region of said VDMOS transistor;

b) doping regions in said epitaxial structure, wherein each of said doping regions comprises a first dopant, wherein each of said doping regions comprises a body region for said VDMOS transistor;

c) a gate oxide layer on said doping region, wherein said gate oxide layer is formed after said body regions are formed;

d) a gate on said gate oxide region, wherein said gate extends to adjacent of said doping regions;

e) a dielectric layer on surfaces of said gate;

f) source regions at either side of said gate in said body regions, wherein said source regions comprise a second dopant having a type that is opposite to that of said first dopant;

g) a contact hole region between said source regions in said body regions, wherein said contact hole comprises a third dopant having a same type as said first dopant; and

h) an aluminum metal layer and a passivation layer on a chip surface.

10. The VDMOS transistor of claim 9 , further comprising a JFET injection layer.

11. The VDMOS transistor of claim 9 , further comprising a depletion layer under said gate oxide layer and covering said active region.

12. The VDMOS transistor of claim 9 , wherein each of said body regions comprises a P-body region.

13. The VDMOS transistor of claim 9 , wherein each of said body regions comprises an N-body region.

14. The VDMOS transistor of claim 9 , further comprising a substrate under said epitaxial structure.

15. The VDMOS transistor of claim 14 , further comprising a drain contact at a bottom of said substrate.

16. A switching voltage regulator, comprising:

a) the VDMOS transistor of claim 9 ; and

b) an inductor coupled to said VDMOS transistor.

17. The method of claim 8 , further comprising forming a drain contact at a bottom of said substrate.