IP Library › Granted Patent US 9,250,935
Granted Patent B2
US 9,250,935 · App. 14/533,540 · Granted Feb 2, 2016

Systems and methods for loop suspension in java programming

Inventors: Haitao Huang (Shanghai, CN); Liping Gao (Shanghai, CN); Xinyu Qi (Shanghai, CN); Ningsheng Jian (Shanghai, CN)
Assignee: MARVELL WORLD TRADE LTD.
G06F9/45508
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Quick Facts
Patent No.
US 9,250,935
App. No.
14/533,540
Filed
Nov 5, 2014
Granted
Feb 2, 2016
Kind
B2
Art Unit
2191
USPC
717/148
Abstract

System and methods are provided for loop process suspension. One or more loop instructions associated with a loop process are loaded in a code cache. One or more branch instructions associated with a branch of the loop process in the code cache are determined. A suspension event is detected. The branch instructions are replaced with one or more jump instructions in the code cache upon the detection of the suspension event. If the jump instructions are executed in the code cache, the branch instructions in the code cache are restored, and the loop process is suspended. One or more suspension instructions associated with the suspension event are executed in an interpreter.

Claims (52)

1. A method comprising:

loading loop instructions, associated with a loop process, into a code cache;

identifying a branch instruction of the loop process in the code cache;

detecting a suspension event;

in response to detecting the suspension event, replacing the branch instruction in the code cache with a jump instruction for jumping to an interpreter configured to execute one or more suspension instructions associated with the suspension event;

continuing program execution until the jump instruction is reached;

when the jump instruction is reached, executing the jump instruction by jumping to the interpreter;

in response to the executing of the jump instruction, restoring the branch instructions in the code cache, and

executing, by the interpreter, the one or more suspension instructions, wherein the restoring of the branch instruction in the code cache is performed before completion of the executing of the one or more suspension instructions; and

returning to execution of the loop process after the executing of the one or more suspension instructions.

2. The method of claim 1 , wherein the branch corresponds to a loop back edge associated with the loop process.

3. The method of claim 1 , further comprising:

setting a suspend flag.

4. The method of claim 3 , wherein the suspend flag is not tested during the loop process.

5. The method of claim 1 , further comprising;

in response to the branch instructions being restored in the code cache, testing a suspend flag; and

in response to the suspend flag not being set, continuing the loop process.

6. The method of claim 1 , wherein the code cache is associated with a Just-in-time (JIT) compiler.

7. The method of claim 1 , wherein the interpreter is associated with a Java virtual machine.

8. A system comprising:

a non-transitory computer-readable medium storing a code cache configured to store one or more loop instructions associated with a loop process;

a data processor configured to execute instructions to implement:

a monitor component configured to identify a branch instruction of the loop process in the code cache,

detect a suspension event; and

in response to detecting the suspension event, replace the branch instructions in the code cache with a jump instruction for jumping to an interpreter configured to execute one or more suspension instructions associated with the suspension event;

a running component configured to continue program execution until the jump instruction is reached;

when the jump instruction is reached, execute the jump instruction by jumping to the interpreter; and

in response to the executing of the jump instruction, restore the branch instructions in the code cache, and

the interpreter configured to execute the one or more suspension instructions, wherein restoring the branch instruction in the code cache is performed before completion of the executing of the one or more suspension instructions; and

a processing engine configured to return to execution of the loop process after the executing of the one or more suspension instructions.

9. The system of claim 8 , wherein the branch corresponds to a loop back edge associated with the loop process.

10. The system of claim 8 , wherein the monitor component is further configured to set a suspend flag.

11. The system of claim 10 , wherein the running component is configured not to test the suspend flag during the loop process.

12. The system of claim 8 , wherein the running component is further configured to:

upon the execution of the branch instructions, test a suspend flag; and in response to the suspend flag not being set, continue the loop process.

13. The system of claim 8 , wherein the code cache is associated with a Just-in-time (JIT) compiler.

14. The system of claim 8 , wherein the interpreter is associated with a Java virtual machine.

15. A system comprising:

a code cache configured to store loop instructions associated with a loop process; and

one or more data processors configured to:

identify a branch instruction of the loop process in the code cache;

detect a suspension event;

in response to detecting the suspension event, replace the branch instruction with a jump instruction for jumping to an interpreter configured to execute one or more suspension instructions associated with the suspension event;

continue program execution until the jump instruction is reached;

when the jump instruction is reached, execute the jump instruction in the code cache;

in response to the executing of the jump instruction, restore the branch instructions in the code cache, and

execute the one or more suspension instructions in an interpreter, wherein restoring the branch instruction in the code cache is performed before completion of the executing of the one or more suspension instructions; and

return to execution of the loop process after the executing of the one or more suspension instructions.

16. The system of claim 15 , wherein the branch corresponds to a loop back edge associated with the loop process.

17. The system of claim 15 , wherein the one or more data processors are further configured to:

upon the restoration of the branch instructions in the code cache, test a suspend flag; and

in response to the suspend flag not being set, continue the loop process.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053475/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2020
From: MARVELL INTERNATIONAL LTD.
To: CAVIUM INTERNATIONAL
Reel/Frame 052918/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2020
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 051778/0537 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2015
From: HUANG, HAITAO; GAO, LIPING; QI, XINYU; JIAN, NINGSHENG
To: MARVELL TECHNOLOGY (SHANGHAI) LTD.
Reel/Frame 034683/0659 →
LICENSE Recorded Jan 12, 2015
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 034683/0845 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2015
From: MARVELL TECHNOLOGY (SHANGHAI) LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 034683/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2015
From: MARVELL INTERNATIONAL LTD.
To: MARVELL WORLD TRADE LTD.
Reel/Frame 034683/0798 →
Continuity (2)
Provisional Application 61908429 · Nov 25, 2013
Related Publication 20150149986A1 · May 28, 2015