Multi channel semiconductor memory device and semiconductor device including the same
Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a shared bus. The semiconductor memory device is capable of reducing an overhead of a die size by reducing the number of through-silicon vias. A method of driving a multi-channel semiconductor memory device including a plurality of memories, using a shared bus, is also provided.
1. A multi-channel semiconductor memory chip comprising:
a first channel memory area configured to receive a first channel command signal through a shared bus during a first time period and receive a first data signals through a first data bus; and
a second channel memory area configured to receive a second channel command signal through the shared bus after the first time period and receive a second data signals through a second data bus,
wherein the first channel command signal is applied to the first channel memory area through the shared bus, and the second channel command signal is applied to the second channel memory area different from the first channel memory area in the multi-channel semiconductor memory chip through the shared bus,
wherein the first a data bus is connected to a first control unit, the second data bus is connected to a second control unit, and the shared bus is commonly connected to the first control unit and the second control unit,
wherein the first data bus provides the first channel memory area with a first column command and a first column address, the second data bus provides the second channel memory area with a second column command and a second column address, and the shared data bus provides both the first channel memory area and the second channel memory area with a first row command and first row addresses.
2. The multi-channel semiconductor memory chip of claim 1 ,
wherein the second channel memory area configured to receive the second channel command signal through the shared bus during a second time period that is not overlapped with the first time period.
3. The multi-channel semiconductor memory chip of claim 1 ,
wherein the first channel command is a row command or a column command.
4. The multi-channel semiconductor memory chip of claim 2 ,
wherein the row command is an active command or a precharge command.
5. The multi-channel semiconductor memory chip of claim 2 ,
wherein the column command is a read command or a write command.
6. The multi-channel semiconductor memory chip of claim 1 ,
wherein the first data bus and the second data bus are configured to have 128 data bits respectively.
7. The multi-channel semiconductor memory chip of claim 1 , further comprising:
the first channel memory area configured to receive a first channel address signal through the shared bus and the second channel memory area configured to receive a second channel address signal through the shared bus.
8. The multi-channel semiconductor memory chip of claim 1 ,
wherein the first data bus is separated from the second data bus.
9. An operating method of a multi-channel semiconductor memory chip comprising:
providing a first channel memory area and a second channel memory area different from the first channel memory area;
providing a first control unit connected to the first channel memory area via a first data bus and a second control unit connected to the second channel memory area via a second data bus, wherein the shared bus is commonly connected to the first control unit and the second control unit;
applying a first channel command signal and a first address signal from the first control unit through a shared bus to operate the first channel memory area during a first time period;
applying a second channel command signal and a second address signal from the second control unit through the shared bus to operate the second channel memory area after the first time period;
receiving or transmitting a first channel data signal of the first channel memory area through a first data bus; and
receiving or transmitting a second channel data signal of the second channel memory area through a second data bus.
10. The operating method of claim 9 ,
wherein the second channel memory area configured to receive the second channel command signal through the shared bus during a second time period that is not overlapped with the first time period.