IP Library › Granted Patent US 9,257,080
Granted Patent B2
US 9,257,080 · App. 13/852,916 · Granted Feb 9, 2016

Display panel driving circuit and display device

Inventor: Hiroshi Tachibana (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
G09G3/3611G09G3/3688G09G2310/0283G09G2370/08
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Quick Facts
Patent No.
US 9,257,080
App. No.
13/852,916
Granted
Feb 9, 2016
Kind
B2
Abstract

A scanning line driving circuit includes an arithmetic circuit for generating an operation result for specifying a unit register for outputting an output signal by means of an arithmetic process on an output number control signal for specifying the number of signals to be outputted. An input stage of each unit register is provided with a signal control circuit for controlling whether to allow the unit register to output an output signal based on the operation result.

Claims (23)

1. A display panel driving circuit, comprising:

a plurality of unit driving circuits for outputting signals to a plurality of scanning lines or a plurality of image signal lines of a display panel; and

an arithmetic circuit for receiving a first control signal for specifying the number of signals to be outputted, and generating a second control signal for specifying a unit driving circuit which outputs a signal, out of said plurality of unit driving circuits according to an arithmetic process on the first control signal, wherein

each of said plurality of unit driving circuits includes a signal control circuit for controlling whether to allow the unit driving circuit to output a signal based on said second control signal,

said first control signal is a pulse signal having a pulse width that varies relative to the number of said signals to be outputted, and

said arithmetic circuit includes:

a counter for counting said pulse width, and

an arithmetic section for generating said second control signal according to an arithmetic process on a counted value of said counter.

2. The display panel driving circuit according to claim 1 , wherein

said plurality of unit driving circuits are cascade-connected, and

from the unit driving circuit at the first stage, unit driving circuits whose number is the same as that of said signals specified by said first control signal are allowed to output.

3. The display panel driving circuit according to claim 1 , wherein

said plurality of unit driving circuits are cascade-connected, and

from the unit driving circuit at the last stage, unit driving circuits whose number is the same as that of said signals specified by said first control signal are allowed to output signals.

4. The display panel driving circuit according to claim 1 , wherein

said plurality of unit driving circuits are cascade-connected, and

a predetermined number of unit driving circuits counted from the first stage and a predetermined number of unit driving circuits counted from the last stage are allowed to output signals so that totally the same number of unit driving circuits as the number of said signals specified by said first control signal are allowed to output signals.

5. A display device, comprising:

a display panel driving circuit according to claim 1 ; and

a timing controller for defining an operation timing of said driving circuit, wherein

said first control signal is supplied from said timing controller.

6. The display device according to claim 5 , wherein

said timing controller generates said first control signal based on a start signal for starting the operations of said plurality of unit driving circuits and an end signal for stopping the operations.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2021
From: MITSUBISHI ELECTRIC CORPORATION
To: TRIVALE TECHNOLOGIES
Reel/Frame 057651/0234 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2013
From: TACHIBANA, HIROSHI
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 030110/0615 →
Priority Claims (1)
JP 2012-097444 · Apr 23, 2012 · national
Continuity (1)
Related Publication 20130278489A1 · Oct 24, 2013