Apparatus and methods for capacitive load reduction
Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes a plurality of power amplifiers and an envelope tracking module for generating a supply voltage for the power amplifiers. The power amplifier system further includes a switch and a decoupling capacitor operatively associated with a first power amplifier of the system. The switch is configured to electrically float an end of the decoupling capacitor when the first power amplifier is disabled so as to reduce capacitive loading of the envelope tracker and to operate as a dampening resistor when the power amplifier is enabled so as to improve the stability of the system.
1. A power amplifier system comprising:
a first power amplifier configured to receive a power amplifier supply voltage, the first power amplifier having an enabled state and a disabled state;
a supply control circuit configured to control a voltage level of the power amplifier supply voltage;
a first switchable capacitor;
a first field effect transistor (FET) electrically connected in series with the first switchable capacitor between the power amplifier supply voltage and a first voltage; and
a power amplifier control circuit configured to control a voltage level of a gate of the first FET, the power amplifier control circuit configured to bias the first FET in a linear mode of operation when the first power amplifier is enabled to provide stability to the first power amplifier, the power amplifier control circuit further configured to turn off the first FET when the first power amplifier is disabled to reduce a capacitive loading of the supply control circuit.
2. The power amplifier system of claim 1 wherein the power amplifier control circuit is further configured to bias the first FET as a dampening resistor when the first power amplifier is enabled.
3. The power amplifier system of claim 2 wherein the power amplifier control circuit is configured to bias a gate of the first FET so as to have a channel resistance in the range of about 0.5Ω to about 2Ω when the first power amplifier is enabled.
4. The power amplifier system of claim 2 wherein the power amplifier control circuit includes a digital-to-analog converter configured to generate a bias signal configured to control the voltage level of the gate of the first FET.
5. The power amplifier system of claim 1 further comprising a second power amplifier configured to receive the power amplifier supply voltage, the second power amplifier having an enabled state and a disabled state.
6. The power amplifier system of claim 5 further comprising a second switchable capacitor and a second FET electrically connected in series between the power amplifier supply voltage and the first voltage, the power amplifier control circuit further configured to bias the second FET in a linear mode of operation when the second power amplifier is enabled, the power amplifier control circuit further configured to turn off the second FET when the second power amplifier is disabled.
7. The power amplifier system of claim 1 wherein the supply control circuit comprises an envelope tracking circuit.
8. The power amplifier system of claim 7 wherein the first power amplifier is configured to amplify a first radio frequency signal when the first power amplifier is enabled, the envelope tracking circuit configured to control the voltage level of the power amplifier supply voltage based at least partly on an envelope of the first radio frequency signal.
9. The power amplifier system of claim 1 wherein the first voltage comprises a ground node.
10. A mobile device comprising:
a first power amplifier configured to receive a power amplifier supply voltage and an input signal, the first power amplifier having an enabled state and a disabled state;
a transceiver configured to generate the input signal;
a supply control circuit configured to control a voltage level of the power amplifier supply voltage;
a first switchable capacitor;
a first field effect transistor (FET) electrically connected in series with the first switchable capacitor between the power amplifier supply voltage and a first voltage; and
a power amplifier control circuit configured to control a voltage level of a gate of the first FET, the power amplifier control circuit configured to bias the first FET in a linear mode of operation when the first power amplifier is enabled to provide stability to the first power amplifier, the power amplifier control circuit further configured to turn off the first FET when the first power amplifier is disabled to reduce a capacitive loading of the supply control circuit.
11. The mobile device of claim 10 wherein the power amplifier control circuit is further configured to bias the first FET as a dampening resistor when the first power amplifier is enabled.
12. The mobile device of claim 10 wherein the supply control circuit comprises an envelope tracking circuit configured to receive an envelope signal from the transceiver, the envelope tracking circuit configured to control the voltage level of the power amplifier supply voltage based on the envelope signal.
13. The mobile device of claim 12 further comprising a battery configured to provide a battery voltage to the envelope tracking circuit.
14. The mobile device of claim 10 further comprising a switch and an antenna, the first power amplifier including an output electrically connected to the antenna through the switch.
15. A multi-chip module comprising:
a first switchable capacitor;
a power amplifier die including a first power amplifier configured to receive a power amplifier supply voltage, the first power amplifier having an enabled state and a disabled state, the power amplifier die further including a first field effect transistor (FET) electrically connected in series with the first switchable capacitor between the power amplifier supply voltage and a first voltage; and
a bias control die including a power amplifier control circuit configured to control a voltage level of a gate of the first FET, the power amplifier control circuit configured to bias the first FET in a linear mode of operation when the first power amplifier is enabled to provide stability to the first power amplifier, the power amplifier control circuit further configured to turn off the first FET when the first power amplifier is disabled.
16. The multi-chip module of claim 15 wherein the power amplifier control circuit is further configured to bias the first FET as a dampening resistor when the first power amplifier is enabled.
17. The multi-chip module of claim 16 wherein the power amplifier control circuit is configured to bias a gate of the first FET so as to have a channel resistance in the range of about 0.5Ω to about 2Ω when the first power amplifier is enabled.
18. The multi-chip module of claim 15 further comprising a second power amplifier die including a second power amplifier configured to receive the power amplifier supply voltage, the second power amplifier having an enabled state and a disabled state.
19. The multi-chip module of claim 18 further comprising a second switchable capacitor, the second FET electrically connected in series with the second switchable capacitor between the power amplifier supply voltage and the first voltage, the power amplifier control circuit further configured to bias the second FET in a linear mode of operation when the second power amplifier is enabled, the power amplifier control circuit further configured to turn off the second FET when the second power amplifier is disabled.
20. The multi-chip module of claim 15 wherein the first switchable capacitor is a surface mount component.