IP Library › Granted Patent US 9,262,308
Granted Patent B2
US 9,262,308 · App. 14/516,259 · Granted Feb 16, 2016

Test paths generation for a physical system

Inventors: Anurag Dwarakanath (Bangalore, IN); Aruna Jankiti (Bangalore, IN)
Assignee: Accenture Global Services Limited
G06F11/3684G06F11/34G06F2201/86
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,262,308
App. No.
14/516,259
Granted
Feb 16, 2016
Kind
B2
Abstract

A system generates a test path set in a very efficient manner. The test path set may be tailored to test a target physical system, such as a complex set of source code, a manufacturing line of multiple process nodes, or other physical system. The system may generate the test path set to meet certain goals in testing the target physical system, for example comprehensive testing of system paths, system nodes, or particular subsets. As one example, the system may efficiently generate a test path set that uses the minimum number of test paths to test a coverage goal, for example traversing each of the prime paths in the target physical system.

Claims (103)

1. A method comprising:

transforming a physical system representation into a system model comprising vertices and edges that represent physical processing flow from a start vertex to an end vertex through the physical system;

storing the system model in a machine-readable memory;

with processing circuitry:

retrieving the system model;

executing a system analysis on the system model to generate a test path set configured to test the physical processing within the physical system; and

through a communication interface, communicating the test path set to a test recipient for testing the physical system;

where the processing circuitry is configured to execute the system analysis by:

determining system paths through the system model;

transforming the system model into a transformed model comprising transformed flows that represent instances where system paths connect to one another;

transforming the transformed model into a flow model comprising model flows by splitting an internal node in the transformed model to separate an incoming flow and an outgoing flow to and from the internal node, where splitting the internal node in the transformed model includes:

selecting the internal node;

replacing the internal node with a first split node, a second split node, and an edge between the first split node and the second split node;

directing the incoming flow to the internal node instead to the first split node; and

making the outgoing flow from the internal node outgoing from the second split node;

selecting specific model flows within the flow model that provide a tour of each system path; and

generating the test path set from the specific model flows.

2. The method of claim 1 , where the processing circuitry is further configured to:

add, to the model flows, the edge between the first and second split nodes.

3. The method of claim 2 , where the processing circuitry is further configured to:

assign a flow condition to the model flows.

4. The method of claim 2 , where the processing circuitry is further configured to:

assign a flow condition to the model flows that ensures that each connection between split internal nodes is chosen among the specific model flows.

5. The method of claim 1 , where the processing circuitry is further configured to:

remove a cycle in the transformed model.

6. The method of claim 1 , where determining system paths comprises:

recognizing a first path type in which no vertex is visited more than once other than the start vertex and end vertex; and

identifying, as a system path, a particular path of the first path type that is not a sub-path of a different path of the first path type.

7. A device comprising:

a communication interface;

transformation circuitry configured to:

transform a physical system representation into a system model comprising vertices and edges that represent physical processing flow from a start vertex to an end vertex through the physical system;

a memory configured to store the system model; and

processing circuitry configured to:

retrieve the system model;

execute a system analysis on the system model to generate a test path set configured to test the physical processing within the physical system; and

communicating the test path set through the communication interface to a test recipient for testing the physical system;

where the processing circuitry is configured to execute the system analysis by:

determining system paths through the system model;

transforming the system model into a transformed model comprising transformed flows that represent instances where system paths connect to one another;

transforming the transformed model into a flow model comprising model flows by splitting an internal node in the transformed model to separate an incoming flow and an outgoing flow to and from the internal node, where splitting the internal node in the transformed model includes:

selecting the internal node;

replacing the internal node with a first split node, a second split node, and an edge between the first split node and the second split node;

directing the incoming flow to the internal node instead to the first split node; and

making the outgoing flow from the internal node outgoing from the second split node;

selecting specific model flows within the flow model that provide a tour of each system path; and

generating the test path set from the specific model flows.

8. The device of claim 7 , where the processing circuitry is further configured to:

add, to the model flows, the edge between the first and second split nodes.

9. The device of claim 8 , where the processing circuitry is further configured to:

assign a flow condition to the model flows.

10. The device of claim 8 , where the processing circuitry is further configured to:

assign a flow condition to the model flows that ensures that each connection between split internal nodes is chosen among the specific model flows.

11. The device of claim 7 , where the processing circuitry is further configured to:

remove a cycle in the transformed model.

12. The device of claim 7 , where determining system paths comprises:

recognizing a first path type in which no vertex is visited more than once other than the start vertex and end vertex; and

identifying, as a system path, a particular path of the first path type that is not a sub-path of a different path of the first path type.

13. A product comprising:

a tangible medium storing instructions, that when executed by a processor, cause the processor to:

transform a physical system representation into a system model comprising vertices and edges that represent physical processing flow from a start vertex to an end vertex through the physical system;

execute a system analysis on the system model to generate a test path set configured to test the physical processing within the physical system; and

through a communication interface, communicate the test path set to a test recipient for testing the physical system;

where the instructions cause the processor to execute the system analysis by:

determining system paths through the system model;

transforming the system model into a transformed model comprising transformed flows that represent instances where system paths connect to one another;

transforming the transformed model into a flow model comprising model flows by splitting an internal node in the transformed model to separate an incoming flow and an outgoing flow to and from the internal node, where splitting the internal node in the transformed model includes:

selecting the internal node;

replacing the internal node with a first split node, a second split node, and an edge between the first split node and the second split node;

directing the incoming flow to the internal node instead to the first split node; and

making the outgoing flow from the internal node outgoing from the second split node;

selecting specific model flows within the flow model that provide a tour of each system path; and

generating the test path set from the specific model flows.

14. The product of claim 13 , where the instructions further cause the processor to:

add, to the model flows, the edge between the first and second split nodes.

15. The product of claim 14 , where the instructions further cause the processor to:

assign a flow condition to the model flows.

16. The product of claim 14 , where the instructions further cause the processor to:

assign a flow condition to the model flows that ensures that each connection between split internal nodes is chosen among the specific model flows.

17. The product of claim 13 , where the instructions further cause the processor to:

remove a cycle in the transformed model.

18. A method comprising:

transforming a physical system representation into a system model comprising vertices and edges that represent physical processing flow from a start vertex to an end vertex through the physical system;

storing the system model in a machine-readable memory;

with processing circuitry:

retrieving the system model;

executing a system analysis on the system model to generate a test path set configured to test the physical processing within the physical system; and

through a communication interface, communicating the test path set to a test recipient for testing the physical system;

where the processing circuitry is configured to execute the system analysis by:

determining system paths through the system model;

transforming the system model into a transformed model comprising transformed flows that represent instances where system paths connect to one another;

transforming the transformed model into a flow model comprising model flows by splitting internal nodes in the transformed model to separate incoming flows and outgoing flows to and from the internal nodes, where splitting comprises, with respect to a selected internal node among the internal nodes:

adding a splitting node;

making an outgoing flow of the selected internal node an outgoing flow from the splitting node instead; and

adding a splitting edge outgoing from the selected internal node and incoming to the splitting node;

selecting specific model flows within the flow model that provide a tour of each system path; and

generating the test path set from the specific model flows.

19. The method of claim 18 , where the processing circuitry is further configured to:

assign a lower flow bound to the splitting edge, the lower flow bound representing a minimum number of flows that traverse the splitting edge.

20. The method of claim 19 where the lower flow bound is set to a value of 1.

21. The method of claim 18 where each of the determined system paths are represented as vertices in the transformed model, and further comprising placing an edge between a first vertex and a second vertex in the transformed model when a particular system path exists, among the determined system paths, that can tour the determined system paths represented by the first and second vertices.

22. The method of claim 18 where determining system paths through the system model comprises:

determining prime paths through the system model, where the prime paths are simple paths that do not appear as a sub-path of any other simple path, and where the prime path does not have repeating vertices other than the start vertex and end vertex.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2014
From: DWARAKANATH, ANURAG; JANKITI, ARUNA
To: ACCENTURE GLOBAL SERVICES LIMITED
Reel/Frame 034002/0985 →
Priority Claims (2)
IN 284/CHE/2014 · Jan 23, 2014 · national
IN 284/CHE/2014 · Aug 27, 2014 · national
Continuity (1)
Related Publication 20150205707A1 · Jul 23, 2015