Driving circuit of a semiconductor display device and the semiconductor display device
There are provided a driving circuit of a semiconductor display device which can obtain an excellent picture without picture blur (display unevenness) and with high fineness/high resolution, and the semiconductor display device. A buffer circuit used in the driving circuit of the semiconductor display device is constituted by a plurality of TFTs each having a small channel width, and a plurality of such buffer circuits are connected in parallel with each other.
1. A display device, comprising:
a pixel matrix circuit; and
a first gate signal line side driving circuit and a second gate signal line side driver circuit, wherein the pixel matrix circuit is located between the first gate signal line side driving circuit and the second gate signal line side driver circuit, each of the first gate signal line side driving circuit and the second gate signal line side driver circuit including a shift register circuit and a buffer circuit electrically connected with the shift register circuit, the buffer circuit comprising an inverter,
wherein the inverter comprises a plurality of n-channel thin film transistors and at least one p-channel thin film transistor,
wherein each of the plurality of n-channel thin film transistors is connected in parallel with each other, and
wherein a channel region of the plurality of n-channel thin film transistors comprises crystalline silicon.
2. The display device according to claim 1 , wherein the display device has an electroluminescence element.
3. The display device according to claim 1 , wherein each of the plurality of n-channel thin film transistors has a plurality of gate electrodes.
4. The display device according to claim 1 , wherein the plurality of n-channel thin film transistors share a first semiconductor film for a channel region thereof.
5. The display device according to claim 1 , wherein the display device is a liquid crystal display device.
6. The display device according to claim 1 , wherein the plurality of n-channel thin film transistors have channel widths of 100 μm or less.
7. A display device, comprising:
a pixel matrix circuit; and
a first gate signal line side driving circuit and a second gate signal line side driver circuit, wherein the pixel matrix circuit is located between the first gate signal line side driving circuit and the second gate signal line side driver circuit, each of the first gate signal line side driving circuit and the second gate signal line side driver circuit including a shift register circuit and a buffer circuit electrically connected with the shift register circuit, the buffer circuit comprising an inverter,
wherein the inverter comprises a plurality of p-channel thin film transistors and at least one n-channel thin film transistor,
wherein each of the plurality of p-channel thin film transistors is connected in parallel with each other, and
wherein a channel region of the plurality of p-channel thin film transistors comprises crystalline silicon.
8. The display device according to claim 7 , wherein the display device has an electroluminescence element.
9. The display device according to claim 7 , wherein each of the plurality of p-channel thin film transistors has a plurality of gate electrodes.
10. The display device according to claim 7 , wherein the plurality of p-channel thin film transistors share a first semiconductor film for a channel region thereof.
11. The display device according to claim 7 , wherein the display device is a liquid crystal display device.
12. The display device according to claim 7 , wherein the plurality of p-channel thin film transistors have channel widths of 100 μm or less.
13. A display device, comprising:
a gate signal line side driving circuit including a shift register circuit,
wherein the gate signal line side driving circuit includes a buffer circuit electrically connected with the shift register circuit, the buffer circuit including a plurality of inverters,
wherein at least one of the plurality of inverters comprises a plurality of n-channel thin film transistors and at least one p-channel thin film transistor, and
wherein each of the plurality of n-channel thin film transistors is connected in parallel with each other.
14. The display device according to claim 13 , wherein the display device has an electroluminescence element.
15. The display device according to claim 13 , wherein each of the plurality of n-channel thin film transistors has a plurality of gate electrodes.
16. The display device according to claim 13 , wherein the p-channel thin film transistor has a plurality of gate electrodes.
17. The display device according to claim 13 , wherein the plurality of n-channel thin film transistors have channel widths of 100 μm or less.
18. A display device, comprising:
a gate signal line side driving circuit including a shift register circuit,
wherein the gate signal line side driving circuit includes a buffer circuit electrically connected with the shift register circuit, the buffer circuit including a plurality of inverters,
wherein at least one of the plurality of inverters comprises a plurality of p-channel thin film transistors and at least one n-channel thin film transistor, and
wherein each of the plurality of p-channel thin film transistors is connected in parallel with each other.
19. The display device according to claim 18 , wherein the display device has an electroluminescence element.
20. The display device according to claim 18 , wherein each of the plurality of p-channel thin film transistors has a plurality of gate electrodes.
21. The display device according to claim 18 , wherein the n-channel thin film transistor has a plurality of gate electrodes.
22. The display device according to claim 18 , wherein the plurality of p-channel thin film transistors have channel widths of 100 μm or less.