Dopant etch selectivity control
Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.
1. A method of etching a substrate, the method comprising:
transferring the substrate into a substrate processing region of a substrate processing chamber;
flowing a fluorine-containing precursor into a remote plasma region fluidly coupled to the substrate processing region while forming a plasma in the remote plasma region to produce plasma effluents;
flowing the plasma effluents into the substrate processing region housing the substrate, wherein the plasma effluents flow into the substrate processing region through perforations in an ion suppression element disposed between the remote plasma region and the substrate processing region; and
etching an n-type silicon portion faster than a p-type silicon portion by flowing the plasma effluents into the substrate processing region, wherein the substrate comprises the n-type silicon portion and the p-type silicon portion.
2. The method of claim 1 wherein the n-type silicon portion is phosphorus-doped.
3. The method of claim 1 wherein the p-type silicon portion is boron-doped.
4. The method of claim 1 wherein etching the n-type silicon portion comprises etching the n-type silicon portion faster than the p-type silicon portion by a multiplicative factor of at least two.
5. The method of claim 1 wherein the n-type silicon portion is below the p-type silicon portion when the substrate is horizontal with n-type silicon portion and p-type silicon portion on top of the substrate.
6. The method of claim 1 wherein a dopant concentration of the n-type silicon portion is greater than or about 10 14 cm −3 .
7. The method of claim 1 wherein a dopant concentration of the p-type silicon portion is greater than or about 10 15 cm −3 .
8. A method of etching a patterned substrate, the method comprising:
transferring the patterned substrate into a substrate processing region of a substrate processing chamber wherein the patterned substrate comprises polysilicon, a gate oxide and an active area of single crystal silicon, wherein the polysilicon is above the gate oxide which is above the active area of single crystal silicon;
flowing a fluorine-containing precursor into a remote plasma region fluidly coupled to the substrate processing region while forming a plasma in the remote plasma region to produce plasma effluents;
flowing the plasma effluents into the substrate processing region housing the patterned substrate, wherein the plasma effluents flow into the substrate processing region through perforations in an ion suppression element disposed between the remote plasma region and the substrate processing region; and
etching the polysilicon and the active area of single crystal silicon with the plasma effluents, wherein the polysilicon is etched at greater than twice the rate of the active area of single crystal silicon.
9. The method of claim 8 wherein the active area of single crystal silicon is n-type and the polysilicon is p-type.
10. The method of claim 8 wherein the polysilicon is exposed on two opposing sides during etching the polysilicon and the active area of single crystal silicon.
11. The method of claim 8 wherein the active area of single crystal silicon is exposed on two opposing sides during etching the polysilicon and the active area of single crystal silicon.
12. The method of claim 8 wherein a width of the active area of single crystal silicon is smaller than a width of the polysilicon following etching the polysilicon and the active area of single crystal silicon.
13. The method of claim 8 wherein a width of the polysilicon is larger than a width of the active area of single crystal silicon by at least 1 nm following etching the polysilicon and the active area of single crystal silicon.
14. The method of claim 8 further comprising forming a conducting wordline which extends to within 20 nm of the active area of single crystal silicon, wherein the conducting wordline is configured to apply charge to the polysilicon by tunneling electrons only through the gate oxide.
15. The method of claim 8 wherein the gate oxide is thermal silicon oxide.