Semiconductor device having a charged insulating layer
A semiconductor device comprises a substrate, an active layer over the substrate, and an insulating layer between the substrate and the active layer. The insulating layer is doped with one of positive charge and negative charge and configured to establish an electric field across the active layer when the semiconductor device is powered.
1. A semiconductor device, comprising:
a substrate;
an active layer over the substrate; and
an insulating layer between the substrate and the active layer, the insulating layer being doped with one of positive charge and negative charge and configured to establish an electric field across the active layer when the semiconductor device is powered;
wherein the active layer includes a source region, a drain region, and a channel region between the source region and the drain region; and
wherein the source and drain regions have a same dopant type as the insulating layer, and the channel region has a different dopant type from the insulating layer.
2. The semiconductor device of claim 1 , wherein the insulating layer includes a material selected from silicon oxide, silicon nitride (Si 3 N 4 ) and aluminum oxide (Al 2 O 3 ).
3. The semiconductor device of claim 1 , wherein the insulating layer includes a material selected from silicon dioxide (SiO 2 ), boron doped silicon glass (BSG), phosphorous doped silicon glass (PSG) and boron and phosphorous doped silicon glass (BPSG).
4. The semiconductor device of claim 1 , wherein the positive charge has a concentration ranging from 1×10 12 cm −3 to 5×10 13 cm −3 .
5. A transistor, comprising:
a substrate;
an insulating layer associated with the substrate, the insulating layer including dopant of a first dopant type;
a source region of the first dopant type on the insulating layer;
a drain region of the first dopant type on the insulating layer;
a channel region of a second dopant type between the source region and the drain region on the insulating layer; and
a gate electrode over the channel region, the gate electrode and the insulating layer establishing an electric field therebetween when the transistor is powered.
6. The transistor of claim 5 , wherein the insulating layer includes a material selected from silicon oxide, silicon nitride (Si 3 N 4 ) and aluminum oxide (Al 2 O 3 ).
7. The transistor of claim 5 , wherein the insulating layer includes a material selected from silicon dioxide (SiO 2 ), boron doped silicon glass (BSG), phosphorous doped silicon glass (PSG) and boron and phosphorous doped silicon glass (BPSG).
8. The transistor of claim 5 , wherein the dopant in the insulating layer has a concentration ranging from 1×10 12 cm −3 to 5×10 13 cm −3 .
9. The transistor of claim 5 , wherein the source and drain regions include dopant of the first dopant type, and the channel region includes dopant of a second dopant type different from the first dopant type.
10. The transistor of claim 9 , wherein dopant of one of the first and second dopant types includes B + , B 2+ , BF + , BF 2 + , P 2+ , P 3+ , P 2 + and P 3 + .
11. The semiconductor device of claim 1 , wherein the positive charge has a concentration ranging from 4×10 12 cm −3 to 10×10 12 cm −3 .
12. The semiconductor device of claim 1 , wherein the positive charge includes B + , B 2+ , BF + , BF 2 + , P 2+ , P 3+ , P 2 + and P 3 + .
13. The semiconductor device of claim 1 , wherein the semiconductor device includes an ultra thin body (UTB) MOS transistor.
14. The semiconductor device of claim 1 , wherein the substrate includes a silicon on insulator (SOI) wafer.