Semiconductor device and manufacturing method thereof
View Patent ↗The present invention relates to a semiconductor device and its manufacturing method. The semiconductor device comprises: a gate structure located on a substrate, Ge-containing semiconductor layers located on the opposite sides of the gate structure, a doped semiconductor layer epitaxially grown between the Ge-containing semiconductor layers, the bottom surfaces of the Ge-containing semiconductor layers located on the same horizontal plane as that of the epitaxial semiconductor layer. The epitaxial semiconductor layer is used as a channel region, and the Ge-containing semiconductor layers are used as source/drain extension regions.
1. A method of manufacturing a semiconductor device, comprising the following steps:
forming a Ge-containing semiconductor layer on a semiconductor substrate;
forming a patterned stack on the Ge-containing semiconductor layer, sequentially comprising from bottom to top a gate dielectric layer and a gate layer on the Ge-containing semiconductor layer;
forming sidewall spacers and dielectric interlayers on the opposite sides of the stack;
removing the gate dielectric layer and the gate layer to expose the underlying Ge-containing semiconductor layer;
removing the exposed Ge-containing semiconductor layer to expose the semiconductor substrate and remaining portions of the Ge-containing semiconductor layer; and
epitaxially growing a doped epitaxial semiconductor layer on the exposed semiconductor substrate between remaining portions of the Ge-containing semiconductor layer by using the remaining portions of the Ge-containing semiconductor layer as a seed layer, wherein a surface of the doped epitaxial semiconductor layer that is in contact with a surface of the substrate is coplanar with a surface of the exposed Ge-containing semiconductor layer that is in contact with the surface of the substrate.
2. The method according to claim 1 , characterized in that the Ge-containing semiconductor layer is a P-type doped Ge epitaxial layer, having a doping concentration of 1E15-1E17 cm −3 .
3. The method according to claim 1 , characterized in that the epitaxial semiconductor layer is an N-type doped Ge epitaxial layer, having a doping concentration of 1E13-1E15 cm −3 .
4. The method according to claim 1 , characterized in that the step of removing the exposed portion of the Ge-containing semiconductor layer to expose at least a portion of the substrate comprises:
removing the exposed Ge-containing semiconductor layer by a reactive ion etching process.
5. The method according to claim 1 , characterized in that both the epitaxial semiconductor layer and the Ge-containing semiconductor layer have a thickness of 5-50 nm.
6. The method according to claim 5 , characterized in that both of the epitaxial semiconductor layer and the Ge-containing semiconductor layer have a thickness of 20 nm.
7. The method according to claim 1 , further comprising:
after forming the epitaxial semiconductor layer,
forming a high K gate dielectric layer and a metal gate layer on the epitaxial semiconductor layer.
8. The method according to claim 7 , characterized in that the high K gate dielectric layer forms a U shape along a bottom and sidewalls of the metal gate layer.