Method for cleaning metal gate surface

1. A method for forming an integrated circuit (IC) structure, comprising:

providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL;

etching the ESL and the dielectric layer to form a trench, a surface of the MG exposed in the trench being oxidized to form a first oxide layer on the MG;

removing the first oxide layer using a H 3 PO 4 solution;

transferring the IC structure to a deposition tool, the surface of the MG being oxidized to form a second oxide layer during the transfer;

baking the IC structure under vacuum at a temperature in a range from about 50° C. to about 500° C.; and

reducing the second oxide layer to a metal included in the MG using a reducing agent.

2. The method of claim 1 , wherein the MG includes aluminum (Al), and wherein the first oxide layer includes aluminum oxide (Al 2 O 3 ).

3. The method of claim 2 , wherein the Al 2 O 3 is removed by the H 3 PO 4 solution using a reaction:

Al 2 O 3 +2H 2 PO 4 − +2H + →2AlPO 4 +3H 2 O

4. The method of claim 1 , wherein the thickness of the first oxide layer is in a range from about 40 Å to about 90 Å.

5. The method of claim 1 , wherein the H 3 PO 4 solution includes H 3 PO 4 dissolved in de-ionized water with a concentration in a range from about 5% to about 25%.

6. The method of claim 1 , wherein the MG includes aluminum (Al), and wherein the first oxide layer and the second oxide layer include Al 2 O 3 .

7. The method of claim 1 , wherein the thickness of the second oxide layer is in a range from about 10 Å to about 30 Å.

8. The method of claim 1 , further comprising:

performing an Ar sputtering process to expand an upper portion of the trench.

9. The method of claim 1 , wherein reducing the second oxide layer includes using a nitrogen/hydrogen (N 2 /H 2 ) plasma.

10. The method of claim 9 , wherein the reducing the second oxide layer includes using a power of the N 2 /H 2 plasma in a range from about 100 W to about 2000 W.

11. The method of claim 9 , wherein the Al 2 O 3 is reduced to Al by a reaction:

Al 2 O 3 +3N 2 /H 2 →2Al+3H 2 O

12. The method of claim 11 , wherein a flow rate of the H 2 is in a range from about 100 sccm to about 500 sccm, and wherein a flow rate of the N 2 is in a range from about 1000 sccm to about 4000 sccm.

13. The method of claim 1 , wherein the reducing the second oxide layer is conducted in a pressure range from about 10 mTorr to about 3000 mTorr.

14. The method of claim 1 , further comprising:

forming a barrier layer conformed to a bottom and walls of the trench;

depositing a metal layer on the barrier layer to fill the trench; and

performing a chemical mechanical polishing (CMP) process to form a contact metal in the trench, the contact metal and the dielectric layer being coplanar after the CMP process.

15. A method for forming an integrated circuit (IC) structure, comprising:

providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL;

etching the ESL and the dielectric layer to form a trench to expose a surface of the MG;

forming a first oxide layer on the surface of the MG;

cleaning the surface of the MG using a H 3 PO 4 solution to remove the first oxide layer to expose the surface;

forming a second oxide layer on the surface of the MG;

cleaning the surface of the MG using a nitrogen/hydrogen (N 2 /H 2 ) plasma to thereby reduce the second oxide layer to a metal included in the MG;

forming a barrier layer conformed to a bottom and walls of the trench;

depositing a metal layer on the barrier layer to fill the trench; and

performing a chemical mechanical polishing (CMP) process to form a contact metal in the trench, the contact metal and the dielectric layer being coplanar after the CMP process.

16. The method of claim 15 , after the cleaning the surface of the MG using the N 2 /H 2 plasma, further comprising:

performing an Ar sputtering process to expand an upper portion of the trench.

17. The method of claim 15 , after the cleaning the surface of the MG using a H 3 PO 4 , solution, further comprising:

rinsing the IC structure using de-ionized water; and

spin drying the IC structure.

18. The method of claim 15 , further comprising heating the IC structure at a temperature in a range from about 50° C. to about 500° C.

19. A method for forming an integrated circuit (IC) structure, comprising:

providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL;

etching the ESL and the dielectric layer to form a trench, a surface of the MG exposed in the trench being oxidized to form a first oxide layer on the MG; and

removing the first oxide layer using a H 3 PO 4 solution;

transferring the IC structure to a deposition tool, the surface of the MG being oxidized to form a second oxide layer during the transfer;

baking the IC structure in the deposition tool at a temperature in a range from about 50° C. to about 500° C.;

reducing the second oxide layer to a metal included in the MG using a nitrogen/hydrogen (N 2 /H 2 ) plasma in the deposition tool;

performing an Ar sputtering process to expand an upper portion of the trench in the deposition tool;

forming a barrier layer conformed to a bottom and walls of the trench in the deposition tool;

depositing a metal layer on the barrier layer to fill the trench in the deposition tool; and

performing a chemical mechanical polishing (CMP) process to form a contact metal in the trench, the contact metal and the dielectric layer being coplanar after the CMP process.

20. The method of claim 19 , wherein the MG includes aluminum (Al), and wherein the first oxide layer and the second oxide layer include Al 2 O 3 .