Through silicon via guard ring
The present disclosure relates to forming a plurality of through silicon vias guard rings proximate the scribes streets of a microelectronic device wafer. The microelectronic device wafer includes a substrate wherein the through silicon via guard ring is fabricated by forming vias extending completely through the substrate. The through silicon via guard rings act as crack arresters, such that defects caused by cracks resulting from the dicing of the microelectronic wafer are substantially reduced or eliminated.
1. A method of forming a guard ring, comprising:
forming a microelectronic device wafer comprising a substrate having a first and a second surface and an interconnect layer disposed on the substrate first surface, the substrate including a plurality of integrated circuits formed proximate the substrate first surface, wherein each of the plurality of the plurality of integrated circuits are separated by at least one dicing street;
forming an interconnect guard ring within the interconnect layer and proximate the dicing street; and
forming a plurality of vias proximate the dicing street and extending from the substrate second surface to the substrate first surface, wherein the plurality of vias abut the interconnect guard ring at the substrate first surface.
2. The method of claim 1 , further comprising cutting through the microelectronic device wafer within said dicing street.
3. A method of forming a guard ring, comprising:
forming a microelectronic device wafer comprising a substrate having a first and a second surface and an interconnect layer disposed on the substrate first surface, the substrate including a plurality of integrated circuits formed proximate the substrate first surface, wherein each of the plurality of integrated circuits are separated by at least one dicing street;
forming a plurality of vias proximate the dicing street and extending from the substrate second surface to the substrate first surface;
filling the plurality of vias prior to the forming of the interconnect layer; and
forming an interconnect guard ring within the interconnect layer and proximate the dicing street to abut the plurality of filled vias at the substrate first surface.
4. The method of claim 3 , further comprising cutting through the microelectronic device wafer within said dicing street.
5. A method of forming a microelectronic die, comprising:
forming a substrate having a first and a second surface and an interconnect layer disposed on the substrate first surface, the substrate including integrated circuits formed proximate the substrate first surface;
forming a plurality of vias proximate at least one edge of the substrate and extending from the substrate first surface to the substrate second surface; and
forming an interconnect guard ring within the interconnect layer and proximate the substrate edge wherein at least one of said plurality of vias substantially abuts said interconnect guard ring at the substrate first surface.
6. The method of claim 5 , wherein the forming the interconnect guard ring comprises forming an interconnect guard ring substantially surrounding the integrated circuits.
7. The method of claim 5 , wherein forming the plurality of vias comprises forming a plurality of vias substantially surrounding the integrated circuits.
8. The method of claim 5 , further comprising filling the plurality of vias.