Source/drain structures and methods of forming same

1. A device comprising:

a gate stack disposed over a substrate;

a source/drain (S/D) feature at least partially embedded within the substrate adjacent the gate stack, the feature including:

a first semiconductor material layer;

a second semiconductor material layer disposed over the first semiconductor material layer, wherein the second semiconductor material layer is a different semiconductor material than the first semiconductor material layer; and

a third semiconductor material layer disposed over the second semiconductor material layer, wherein the third semiconductor material layer includes a tin (Sn) material.

2. The device of claim 1 , wherein the first semiconductor material layer is completely embedded in the substrate.

3. The device of claim 1 , wherein the first semiconductor material layer physically contacts the second semiconductor material layer, and

wherein the third semiconductor material layer physically contacts the second semiconductor material layer.

4. The device of claim 1 , wherein:

the first semiconductor material layer includes epitaxially grown silicon germanium (SiGe x1 ), where x 1 is Ge composition in atomic percent;

the second semiconductor material layer includes semiconductor materials from the group consisting of epitaxially grown epitaxially grown silicon germanium (SiGe x2 ) and epitaxially grown silicon germanium tin (SiGe x3 Sn y ), where x 2 and x 3 are Ge composition in atomic percent and y is Sn composition in atomic percent;

the third semiconductor material layer includes semiconductor materials from the group consisting of epitaxially grown germanium tin (GeSn z ), silicon germanium tin (SiGeSn z ), silicon germanium tin boron (SiGeSn z B), and germanium tin boron (GeSn z ), where z is Sn composition in atomic percent;

a thickness of the first semiconductor material layer is in a range of about 5 nm to about 30 nm;

a thickness of the second semiconductor material layer is in a range of about 20 nm to about 60 nm; and

a thickness of the third semiconductor material layer is in a range of about 5 nm to about 30 nm.

5. The device of claim 4 , wherein:

the x 1 in the first semiconductor material layer is substantial constant, which is in a range of about 10% to about 30%;

the x 2 in the second semiconductor material layer is substantial constant, which is in a range of about 30% to about 100%;

the x 3 in the second semiconductor material layer is in a range of about 85% to about 99%;

y in the second semiconductor material layer is in a range of about 1% to about 10%; and

the z in the third semiconductor material layer is in a range of about 1% to about 30%.

6. The device of claim 4 , wherein the x 1 in the first semiconductor material layer is in a grading manner, which changes from about 10% to about 15% (from a bottom to a top of the first semiconductor material layer).

7. The device of claim 4 , wherein the x 2 in the second semiconductor material layer is in a grading manner, which changes from about 35% to about 70% (from a bottom to a top of the first semiconductor material layer).

8. The device of claim 1 , wherein the substrate includes silicon.

9. A fin-like field-effect transistor (FinFET) device comprising:

a substrate having multiple first isolation regions;

a common mesa and multiple fins between two adjacent first isolation regions;

a single source/drain (S/D) feature over the common mesa, the single S/D feature including:

a first semiconductor material layer over the recesses;

a second semiconductor material layer over the first semiconductor material layer, wherein the second semiconductor material layer is different semiconductor material to the first semiconductor material layer; and

a third semiconductor material layer disposed over the second semiconductor material layer, wherein the third semiconductor material layer includes a tin (Sn) material; and

multiple high-k/metal gate (HK/MG) stacks over respective fins, including wrapping over a portion of the fin, wherein the single S/D feature serves as a common S/D for the multiple HK/MG stacks.

10. The device of claim 9 , wherein the first semiconductor material layer is completely embedded in the substrate.

11. The device of claim 10 , wherein the first semiconductor material layer physically contacts the second semiconductor material layer, and

wherein the third semiconductor material layer physically contacts the second semiconductor material layer.

12. The device of claim 9 , wherein:

the first semiconductor material layer includes epitaxially grown silicon germanium (SiGe x1 ), where x 1 is Ge composition in atomic percent;

the second semiconductor material layer includes semiconductor materials from the group consisting of epitaxially grown epitaxially grown silicon germanium (SiGe x2 ) and epitaxially grown silicon germanium tin (SiGe x3 Sn y ), where x 2 and x 3 are Ge composition in atomic percent and y is Sn composition in atomic percent;

the third semiconductor material layer includes semiconductor materials from the group consisting of epitaxially grown germanium tin (GeSn z ), silicon germanium tin (SiGeSn 1 ), silicon germanium tin boron (SiGeSn z B), and germanium tin boron (GeSn z ), where z is Sn composition in atomic percent;

a thickness of the first semiconductor material layer is in a range of about 5 nm to about 30 nm;

a thickness of the second semiconductor material layer is in a range of about 20 nm to about 60 nm; and

a thickness of the third semiconductor material layer is in a range of about 5 nm to about 30 nm.

13. The device of claim 12 , wherein:

the x 1 in the first semiconductor material layer is substantial constant, which is in a range of about 10% to about 30%;

the x 2 in the second semiconductor material layer is substantial constant, which is in a range of about 30% to about 100%;

the x 3 in the second semiconductor material layer is in a range of about 85% to about 99%;

the y in the second semiconductor material layer is in a range of about 1% to about 10%; and

the z in the third semiconductor material layer is in a range of about 1% to about 30%.

14. The device of claim 12 , wherein the x 1 in the first semiconductor material layer is in a grading manner, which changes from about 10% to about 15% (from a bottom to a top of the first semiconductor material layer).

15. The device of claim 12 , wherein the x 2 in the second semiconductor material layer is in a grading manner, which changes from about 35% to about 70% (from a bottom to a top of the first semiconductor material layer).

16. The device of claim 9 , further comprising:

a plurality of fins over the substrate, separated each other by second isolation regions, wherein the second isolation regions are between two adjacent first isolation regions, wherein the first isolation region are deeper than the second isolation region.

17. The device of claim 9 , wherein the substrate includes silicon.

18. A fin-like field-effect transistor (FinFET) device comprising:

a gate stack formed over a substrate;

a source/drain (S/D) feature formed adjacent to the gate stack, the feature including a first semiconductor material layer;

a second semiconductor material layer disposed over the first semiconductor material layer and in contact with the first semiconductor material layer, wherein the second semiconductor material layer is a different semiconductor material than the first semiconductor material layer; and

a third semiconductor material layer disposed over the second semiconductor material layer and in contact with the second semiconductor material layer, wherein the third semiconductor material layer includes a tin (Sn) material.

19. The device of claim 18 , wherein the first semiconductor material layer is completely embedded in the substrate.

20. The device of claim 18 , wherein the first semiconductor material layer includes epitaxially grown silicon germanium (SiGe x1 ), where x 1 is Ge composition in atomic percent,

wherein the second semiconductor material layer includes semiconductor materials from the group consisting of epitaxially grown epitaxially grown silicon germanium (SiGe x2 ) and epitaxially grown silicon germanium tin (SiGe x3 Sn y ), where x 2 and x 3 are Ge composition in atomic percent and y is Sn composition in atomic percent,

wherein the third semiconductor material layer includes semiconductor materials from the group consisting of epitaxially grown germanium tin (GeSn z ), silicon germanium tin (SiGeSn z ), silicon germanium tin boron (SiGeSn z B), and germanium tin boron (GeSn z ), where z is Sn composition in atomic percent.