Split gate flash memory structure with a damage free select gate and a method of making the split gate flash memory structure

1. A method of manufacturing a semiconductor structure of a pair of split gate flash memory cells, said method comprising:

forming a pair of select gates spaced on a semiconductor substrate;

forming a sacrificial spacer filling a central region between the select gates;

forming a charge trapping dielectric layer conformally along sidewalls of the select gates and over top surfaces of the sacrificial spacer and the select gates; and

forming a pair of memory gates corresponding to the pair of select gates over and laterally abutting the charge trapping dielectric layer.

2. The method according to claim 1 , further including:

forming the charge trapping dielectric layer to extend linearly over the central region between the select gates.

3. The method according to claim 1 , further including:

removing portions of the charge trapping dielectric layer formed over top surfaces of the select gates and the sacrificial spacer, while leaving portions of the charge trapping dielectric layer arranged between neighboring sidewalls of the select gates and the memory gates and arranged between the semiconductor substrate and the memory gates; and

removing the sacrificial spacer subsequent to removing the portions.

4. The method according to claim 1 , further including:

forming a liner conformally lining the central region; and

forming the sacrificial spacer over the liner and filling the central region.

5. The method according to claim 4 , further including:

forming the liner from a dielectric material; and

forming the sacrificial spacer from a conductive material.

6. The method according to claim 4 , further including:

forming the liner and the sacrificial spacer with top surfaces approximately coplanar with top surfaces of the select gates.

7. The method according to claim 4 , further including:

removing the sacrificial spacer from the central region subsequent to forming the charge trapping dielectric layer;

forming in the central region a pair of spaced central sidewall structures corresponding to the pair of select gates over and laterally abutting the liner; and

forming outside the central region a pair of peripheral sidewall structures corresponding to the pair of memory gates over the semiconductor substrate and laterally abutting the charge trapping dielectric layer.

8. The method according to claim 7 , further including:

forming the central sidewall structures over a first dielectric region having a greater thickness than a second dielectric region over which the peripheral sidewall structures are formed, the first and second dielectric regions extending from approximately even with a top surface of the semiconductor substrate to approximately even with bottom surfaces of the central sidewall structures and the peripheral sidewall structures, respectively.

9. The method according to claim 7 , further including:

forming the peripheral sidewall structures abutting a top surface of the semiconductor substrate.

10. The method according to claim 7 , further including:

forming a pair of sidewall sealers corresponding to the memory gates over the charge trapping dielectric layer and laterally abutting both the corresponding memory gates and corresponding peripheral sidewall structures.

11. An integrated circuit (IC) including a pair of split gate flash memory cells, said IC comprising:

a semiconductor substrate including first and second individual source/drain regions arranged on opposite sides of a common source/drain region;

first and second select gates arranged over the semiconductor substrate between the first and second individual source/drain regions and arranged on opposite sides of the common source/drain region;

first and second memory gates arranged over the semiconductor substrate and respectively arranged between the first and second individual source/drain regions and the first and second select gates;

first and second peripheral sidewall structures respectively arranged between the first and second individual source/drain regions and the first and second memory gates; and

first and second central sidewall structures respectively arranged between the common source/drain region and the first and second select gates, wherein bottom surfaces of the first and second central sidewall structures are arranged farther above the semiconductor substrate than bottom surfaces of the first and second peripheral sidewall structure.

12. The IC of claim 11 , further including:

first and second charge trapping dielectrics respectively arranged between neighboring sidewalls of the first and second memory and select gates, and respectively arranged under the first and second memory gates;

a first dielectric region extending from a top surface of the semiconductor substrate to the bottom surfaces of the first and second central sidewall structures; and a second dielectric region extending from the top surface of the semiconductor substrate to the bottom surfaces of the first and second peripheral sidewall structures, wherein a thickness of the first dielectric region is greater than a thickness of the second dielectric region.

13. An integrated circuit (IC) including a split gate flash memory cell, said IC comprising:

a semiconductor substrate including first and second source/drain regions;

a select gate arranged over the semiconductor substrate, and having an outer sidewall proximate to the second source/drain and an inner sidewall proximate to the first source/drain region;

a memory gate arranged over the semiconductor substrate between the first source/drain region and the inner sidewall of the select gate, and having an outer sidewall proximate to the first source/drain region and an inner sidewall proximate to the inner sidewall of the select gate;

a charge trapping dielectric arranged between the inner sidewalls of the memory and select gates, and arranged under the memory gate;

a peripheral sidewall structure arranged over the semiconductor substrate between the outer sidewall of the memory gate and the first source/drain region; and

a central sidewall structure arranged over the semiconductor substrate between the outer sidewall of the select gate and the second source/drain region, wherein a bottom surface of the central sidewall structure is arranged farther above the semiconductor substrate than a bottom surface of the peripheral sidewall structure.

14. The IC according to claim 13 , wherein the peripheral sidewall structure abuts a sidewall of the charge trapping dielectric.

15. The IC according to claim 13 , wherein the peripheral sidewall structure abuts a top surface of the semiconductor substrate.

16. The IC according to claim 13 , further including:

a sidewall sealer formed over the charge trapping dielectric and laterally abutting the memory gate and the peripheral sidewall structure.

17. The IC according to claim 13 , wherein the semiconductor substrate further includes a third source/drain region arranged on an opposite side of the second source/drain region as the first source/drain region, and wherein the IC further includes:

a second select gate arranged over the semiconductor substrate, and having an outer sidewall proximate to the second source/drain and an inner sidewall proximate to the third source/drain region;

a second memory gate arranged over the semiconductor substrate between the third source/drain region and the inner sidewall of the second select gate, and having an outer sidewall proximate to the third source/drain region and an inner sidewall proximate to the inner sidewall of the select gate;

a second charge trapping dielectric arranged between the inner sidewalls of the second memory and select gates, and arranged under the second memory gate;

a second peripheral sidewall structure arranged over the semiconductor substrate between the outer sidewall of the second memory gate and the third source/drain region; and

a second central sidewall structure arranged over the semiconductor substrate between the outer sidewall of the second select gate and the second source/drain region, wherein a bottom surface of the second central sidewall structure is arranged farther above the semiconductor substrate than a bottom surface of the second peripheral sidewall structure.

18. The IC according to claim 13 , further including:

a central sidewall dielectric arranged between the central sidewall structure and the semiconductor substrate; and

a peripheral sidewall dielectric arranged between the peripheral sidewall structure and the semiconductor substrate, wherein a dielectric thickness of the central sidewall dielectric between the central sidewall structure and the semiconductor substrate is greater than a dielectric thickness of the peripheral sidewall dielectric between the peripheral sidewall structure and the semiconductor substrate.

19. The IC according to claim 18 , wherein the central sidewall dielectric is further arranged between neighboring sidewalls of the select gate and the central sidewall structure.

20. The IC according to claim 18 , wherein the peripheral sidewall dielectric is a native oxide.