High voltage driver using low voltage transistor
A high voltage driver may include: a low side switching unit including first to n-th N-channel metal oxide semiconductor (NMOS) transistors; a high side switching unit including first and second to n-th P-channel MOS (PMOS) transistors; a voltage dividing unit dividing a voltage between the output terminal and the ground; a first constant voltage unit providing a constant voltage and a unidirectional signal path between a source and a gate of each of the first to n-th NMOS transistors; a second constant voltage unit providing a constant voltage and a unidirectional signal path between a source and a gate of each of the first to n-th PMOS transistors; a first charging unit providing a charged voltage to each of the gates of the second to n-th NMOS transistors; and a second charging unit providing a charged voltage to each of the gates of the second to n-th PMOS transistors.
1. A high voltage driver comprising:
a low side switching unit including first and second to n-th N-channel metal oxide semiconductor (NMOS) transistors connected to each other in series between an output terminal and a ground and operated in a turned-on or turned-off state depending on a first control signal;
a high side switching unit including first and second to n-th P-channel MOS (PMOS) transistors connected to each other in series between a power supply voltage terminal and the output terminal and operated complementarily to the low side switching unit depending on a second control signal;
a voltage dividing unit dividing a voltage between the output terminal and the ground and providing the divided voltages to connection nodes between the first and second to n-th PMOS transistors and connection nodes between the first and second to n-th NMOS transistors, respectively;
a first constant voltage unit providing a constant voltage and a unidirectional signal path between a source and a gate of each of the second to n-th NMOS transistors;
a second constant voltage unit providing a constant voltage and a unidirectional signal path between a source and a gate of each of the second to n-th PMOS transistors;
a first charging unit charged with a voltage through the signal path of the first constant voltage unit and providing the charged voltage to each of the gates of the second to n-th NMOS transistors; and
a second charging unit charged with a voltage through the signal path of the second constant voltage unit and providing the charged voltage to each of the gates of the second to n-th PMOS transistors.
2. The high voltage driver of claim 1 , wherein the first NMOS transistor is operated in the turned-on or turned-off state depending on the first control signal, and
the second to n-th NMOS transistors are operated in synchronization with an operational state of the first NMOS transistor.
3. The high voltage driver of claim 1 , wherein the first PMOS transistor is operated in the turned-on or turned-off state depending on the second control signal, and
the second to n-th PMOS transistors are operated in synchronization with an operational state of the first PMOS transistor.
4. The high voltage driver of claim 1 , wherein the voltage dividing unit includes first to n-th resistors connected to each other in series between the output terminal and the ground and having the same resistance value in order to uniformly divide the voltage.
5. The high voltage driver of claim 1 , wherein the first constant voltage unit includes a plurality of diodes connected between the sources and the gates of the second to n-th NMOS transistors, respectively, in a forward direction.
6. The high voltage driver of claim 1 , wherein the second constant voltage unit includes a plurality of diodes connected between the sources and the gates of the second to n-th PMOS transistors, respectively, in a forward direction.
7. The high voltage driver of claim 1 , wherein the first charging unit includes a plurality of capacitors connected between the gates of the second to n-th NMOS transistors and the ground, respectively, and providing the charged voltage.
8. The high voltage driver of claim 1 , wherein the second charging unit includes a plurality of capacitors connected between the gates of the second to n-th PMOS transistors and the ground, respectively, and providing the charged voltage.
9. A high voltage driver comprising:
a control signal generating unit generating a first control signal having a high level and a low level based on a ground level and a second control signal having an opposite phase to that of the first control signal and having a high level and a low level based on a power supply voltage;
a low side switching unit including first and second to n-th NMOS transistors connected to each other in series between an output terminal and a ground and operated in a turned-on or turned-off state depending on the first control signal;
a high side switching unit including first and second to n-th PMOS transistors connected to each other in series between a power supply voltage terminal and the output terminal and operated in a turn-off or turn-on state depending on the second control signal;
a voltage dividing unit dividing a voltage between the output terminal and the ground and providing the divided voltages to connection nodes between the first and second to n-th PMOS transistors and connection nodes between the first and second to n-th NMOS transistors, respectively;
a second constant voltage unit providing a constant voltage and a unidirectional signal path between a source and a gate of each of the second to n-th PMOS transistors;
a first constant voltage unit providing a constant voltage and a unidirectional signal path between a source and a gate of each of the second to n-th NMOS transistors;
a second charging unit charged with a voltage through the signal path of the second constant voltage unit and providing the charged voltage to each of the gates of the second to n-th PMOS transistors; and
a first charging unit charged with a voltage through the signal path of the first constant voltage unit and providing the charged voltage to each of the gates of the second to n-th NMOS transistors.
10. The high voltage driver of claim 9 , wherein the first NMOS transistor is operated in the turned-on or turned-off state depending on the first control signal, and
the second to n-th NMOS transistors are operated in synchronization with an operational state of the first NMOS transistor.
11. The high voltage driver of claim 9 , wherein the first PMOS transistor is operated in the turned-on or turned-off state depending on the second control signal, and
the second to n-th PMOS transistors are operated in synchronization with an operational state of the first PMOS transistor.
12. The high voltage driver of claim 9 , wherein the voltage dividing unit includes first to n-th resistors connected to each other in series between the output terminal and the ground and having the same resistance value in order to uniformly divide the voltage.
13. The high voltage driver of claim 9 , wherein the first constant voltage unit includes a plurality of diodes connected between the sources and the gates of the second to n-th NMOS transistors, respectively, in a forward direction.
14. The high voltage driver of claim 9 , wherein the second constant voltage unit includes a plurality of diodes connected between the sources and the gates of the second to n-th PMOS transistors, respectively, in a forward direction.
15. The high voltage driver of claim 9 , wherein the first charging unit includes a plurality of capacitors connected between the gates of the second to n-th NMOS transistors and the ground, respectively, and providing the charged voltage.
16. The high voltage driver of claim 9 , wherein the second charging unit includes a plurality of capacitors connected between the gates of the second to n-th PMOS transistors and the ground, respectively, and providing the charged voltage.
17. A high voltage driver comprising:
a control signal generating unit generating a first control signal having a high level and a low level based on a ground level and a second control signal having an opposite phase to that of the first control signal and having a high level and a low level based on a power supply voltage;
a low side switching unit including first and second to n-th NMOS transistors connected to each other in series between an output terminal and a ground and operated in a turned-on or turned-off state depending on the first control signal;
a high side switching unit including first and second to n-th PMOS transistors connected to each other in series between a power supply voltage terminal and the output terminal and operated in a turn-off or turn-on state depending on the second control signal;
a voltage dividing unit dividing a voltage between the output terminal and the ground and providing the divided voltages to connection nodes between the first and second to n-th PMOS transistors and connection nodes between the first and second to n-th NMOS transistors, respectively;
a second constant voltage unit providing a constant voltage and a unidirectional signal path between a source and a gate of each of the second to n-th PMOS transistors;
a first constant voltage unit providing a constant voltage and a unidirectional signal path between a source and a gate of each of the second to n-th NMOS transistors;
a second charging unit charged with a voltage through the signal path of the second constant voltage unit and providing the charged voltage to each of the gates of the second to n-th PMOS transistors;
a first charging unit charged with a voltage through the signal path of the first constant voltage unit and providing the charged voltage to each of the gates of the second to n-th NMOS transistors; and
a signal synchronizing unit connected between terminals of the control signal generating unit outputting the first and second control signal.
18. The high voltage driver of claim 17 , wherein the first NMOS transistor is operated in the turned-on or turned-off state depending on the first control signal, and the second to n-th NMOS transistors are operated in synchronization with an operational state of the first NMOS transistor, and
the first PMOS transistor is operated in the turned-on or turned-off state depending on the second control signal, and the second to n-th PMOS transistors are operated in synchronization with an operational state of the first PMOS transistor.
19. The high voltage driver of claim 17 , wherein the first constant voltage unit includes a plurality of diodes connected between the sources and the gates of the second to n-th NMOS transistors, respectively, in a forward direction, and
the second constant voltage unit includes a plurality of diodes connected between the sources and the gates of the second to n-th PMOS transistors, respectively, in a forward direction.
20. The high voltage driver of claim 17 , wherein the first charging unit includes a plurality of capacitors connected between the gates of the second to n-th NMOS transistors and the ground, respectively, and providing the charged voltage, and
the second charging unit includes a plurality of capacitors connected between the gates of the second to n-th PMOS transistors and the ground, respectively, and providing the charged voltage.