Dynamic RAM Phy interface with configurable power states
A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.
1. A method of controlling a physical memory interface for a memory device, the method comprising:
responsive to receiving a power context change request, selecting a power context based on the power context change request; and
configuring a plurality of adjustable delay elements to provide timing delays for reading data from and writing data to the memory device, each adjustable delay element having a delay time corresponding to the power context.
2. The method of claim 1 includes configuring a plurality of drivers each having a drive strength corresponding to the power context.
3. The method of claim 1 wherein said power context is one of a plurality of power contexts corresponding to a plurality of power states such that selecting the power context in response to the power context change requests results in changing power demand.
4. The method of claim 1 includes configuring a plurality of receivers each having a termination impedance corresponding to the power context.
5. The method of claim 1 wherein selecting the power context includes selecting a set of physical memory interface parameters associated with a power state.
6. The method of claim 2 includes configuring a plurality of receivers each having a termination impedance corresponding to the power context.
7. The method of claim 1 wherein:
selecting the power context includes selecting a set of physical memory interface parameters associated with a power state and;
said physical memory interface parameters include delay time parameters, drive strength parameters and termination impedance parameters.
8. A physical memory interface for a memory device, the physical memory interface comprising:
a plurality of registers configured to store at least two power contexts;
selection circuitry for selecting one of the at least two power contexts; and
a plurality of adjustable elements for providing varying levels of performance for accessing the memory device, each adjustable element is configured to a level of performance by a physical memory interface parameter corresponding to the selected power context.
9. The physical memory interface of claim 8 , wherein the plurality of adjustable elements includes a plurality of adjustable delay elements to provide timing delays for reading data from and writing data to the memory device, each adjustable delay element having a delay time corresponding to the selected power context.
10. The physical memory interface of claim 9 , wherein the plurality of adjustable elements includes a plurality of drivers each having a drive strength corresponding to the selected power context.
11. The physical memory interface of claim 10 , wherein the plurality of adjustable elements includes a plurality of receivers each having a termination impedance corresponding to the selected power context.
12. The physical memory interface of claim 10 , wherein:
the selected power context includes a set of physical memory interface parameters associated with a power state and;
the physical memory interface parameters include delay time parameters, drive strength parameters and termination impedance parameters.
13. The physical memory interface of claim 8 , wherein the plurality of adjustable elements includes a plurality of drivers each having a drive strength corresponding to the selected power context.
14. The physical memory interface of claim 8 , wherein the plurality of adjustable elements includes a plurality of receivers each having a termination impedance corresponding to the selected power context.
15. The physical memory interface of claim 8 , wherein the selected power context is associated with a power state.
16. The physical memory interface of claim 8 , wherein said at least two power contexts are a plurality of power contexts corresponding to a plurality of power states such that selecting the power context results in changing power demand.
17. A computer readable non-transitory medium including instructions which when executed in a processing system cause the system to provide control of a physical memory interface for a memory device comprising:
responsive to receiving a power context change request, selecting a power context based on the power context change request; and
configuring a plurality of adjustable delay elements to provide timing delays for reading data from and writing data to the memory device, each adjustable delay element having a delay time corresponding to the power context.
18. The medium of claim 17 includes configuring a plurality of drivers each having a drive strength corresponding to the power context.
19. The medium of claim 18 includes configuring a plurality of receivers each having a termination impedance corresponding to the power context.
20. The medium of claim 17 includes configuring a plurality of receivers each having a termination impedance corresponding to the power context.