Semiconductor integrated circuit

1. A method of a semiconductor integrated circuit comprising a logic circuit including n storage elements (n is a positive integer) which can each store 1-bit information and an attack detection circuit, the method comprising:

detecting, by an error determination circuit, through a logic operation that k-bit or less errors (k is a positive integer) have occurred in n-bit codes stored in the n storage elements;

detecting, by a light irradiation detection circuit which includes light detection elements, that light has been irradiated to (k+1) or more of the n storage elements; and

determining that the logic circuit has been attacked from outside when the error determination circuit detects an error or the light irradiation detection circuit detects light irradiation.

2. The method according to claim 1 , further comprising:

storing, by the n storage elements including m storage elements, m-bit error detection codes; and

generating, by the error determination circuit including an error detection code generation circuit, an error detection code from (n-m) storage elements of the n storage elements and a check circuit which can detect occurrence of an error in the n storage elements.

3. The method according to claim 1 , further comprising:

storing, by the n storage elements including one storage element, a 1-bit parity code and the light irradiation detection circuit includes (n−1) light detection elements;

generating, by the error determination circuit comprising a parity code generation circuit, the parity code from (n−1) storage elements of the n storage elements;

detecting, by a parity check circuit, an occurrence of an error in the n storage elements; and

detecting, by the light irradiation detection circuit, an occurrence of an error for detecting that light has been irradiated to two or more of the n storage elements at the time of detecting that light has been irradiated to at least one of the (n−1) light detection elements.

4. The method according to claim 3 , wherein arbitrary two storage elements selected from the n storage elements are necessarily disposed with at least one light detection element interposed therebetween.

5. The method according to claim 4 , wherein the (n−1) light detection elements and the n storage elements are each alternately adjacently disposed in a single cell row.

6. The method according to claim 1 ,

wherein the n storage elements comprise m active storage elements which are outputs of an active logic circuit and m backup storage elements which are outputs of a backup logic circuit duplexed with the active circuit;

further comprising:

detecting, by the error determination circuit, that an error has occurred if an output of an active storage element does not match an output of a corresponding backup storage element, and

wherein in the active storage elements and the corresponding backup storage elements, corresponding two storage elements are disposed with at least one light detection element interposed therebetween.

7. The method according to claim 1 ,

wherein the logic circuit comprises a processor, and

wherein the n storage elements comprises a program counter of the processor.

8. The method according to claim 1 ,

wherein the logic circuit comprises a processor, and

further comprising providing, by the n storage elements, by a register, a condition to which the processor refers at the time of executing a conditional branch instruction.

9. The method according to claim 1 ,

wherein the logic circuit comprises a processor, and

wherein the n storage elements comprise a general-purpose register of the processor.

10. The method according to claim 1 ,

wherein the logic circuit comprises a processor, and

further comprising inputting an output of the attack detection circuit to a reset terminal of the processor.

11. The method according to claim 1 ,

wherein the logic circuit comprises a processor including a memory,

further comprising:

generating, by the attack detection circuit, an interrupt to the processor; and

deleting, by the processor, information stored in the memory upon detecting the attack.

12. The method according to claim 1 , further comprising controlling, by a power supply circuit including a power supply control terminal, power supply to the logic circuit,

wherein an output of the attack detection circuit is coupled to the power supply control terminal of the power supply circuit; and

shutting off, by the power supply to the logic circuit, upon detecting the attack.

13. A method of semiconductor integrated circuit comprising a logic circuit including n storage elements (n is a positive integer) which can each store 1-bit information and an attack detection circuit, the attack detection circuit comprising an error determination circuit and a light irradiation detection circuit having light detection elements, the method comprising:

detecting, by the error determination circuit, through a logic operation that k-bit or less errors (k is a positive integer) have occurred in n-bit codes stored in the n storage elements,

wherein a plurality of areas surrounding arbitrary (k+1) storage elements of the n storage elements, with a minimum closed curve having no inward convex circumference, each contain at least one light detection element, and the light irradiation detection circuit detects light irradiation to (k+1) or more of the n storage elements at the time of detecting that light has been irradiated to at least one of the light detection elements; and

determining that the logic circuit has been attacked from outside when the error determination circuit detects an error or the light irradiation detection circuit detects light irradiation.

14. A method of an attack detection circuit, the method comprising:

detecting through a logic operation that k-bit or less errors (k is a positive integer) have occurred in n-bit codes stored in n storage elements (where n is a positive integer) which can each store 1-bit information;

detecting that light has been irradiated to (k+1) or more of the n storage elements; and

determining that a logic circuit including the n storage elements has been attacked from outside when detecting an error or detecting light irradiation.

15. The method according to claim 14 , further comprising:

storing, by the n storage elements including m storage elements, m-bit error detection codes;

generating an error detection code from (n-m) storage elements of the n storage elements and a check circuit; and

detecting an occurrence of an error in the n storage elements.

16. The method according to claim 14 , further comprising:

storing, by the n storage elements including one storage element, a 1-bit parity code, wherein the light irradiation detection circuit includes (n−1) light detection elements; and

generating the parity code from (n−1) storage elements of the n storage elements;

detecting an occurrence of an error in the n storage elements; and

detecting an occurrence of an error for detecting that light has been irradiated to two or more of the n storage elements at the time of detecting that light has been irradiated to at least one of the (n−1) light detection elements.

17. The method according to claim 16 , wherein arbitrary two storage elements selected from the n storage elements are necessarily disposed with at least one light detection element interposed therebetween.

18. The method according to claim 14 ,

wherein the n storage elements comprise m active storage elements which are outputs of an active logic circuit and m backup storage elements which are outputs of a backup logic circuit duplexed with the active circuit,

further comprising:

detecting that an error has occurred if an output of an active storage element does not match an output of a corresponding backup storage element, and

wherein in the active storage elements and the corresponding backup storage elements, corresponding two storage elements are disposed with at least one light detection element interposed therebetween.

19. The method according to claim 14 , wherein the (n−1) light detection elements and the n storage elements are each alternately adjacently disposed in a single cell row.

20. The method according to claim 14 ,

wherein the logic circuit comprises a processor, and

further comprising providing, by the n storage elements, by a register, a condition to which the processor refers at the time of executing a conditional branch instruction.