Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry
A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.
1. A semiconductor structure, comprising:
an NFET device having a P-well at a top side of a substrate;
a PFET device having an N-well at the top side of the substrate; and
a substrate contact comprising a through wafer via extending from a backside of the substrate to a bottom surface of an isolation structure located between the NFET device and the PFET device,
wherein the isolation structure comprises a shallow trench isolation (STI) structure and an isolation feature that abuts and extends below the STI structure.
2. The semiconductor structure of claim 1 , wherein the through wafer via is in contact with and at substantially a same electrical potential as one of the P-well and the N-well, and is remote from the other of the P-well and the N-well, respectively.
3. The semiconductor structure of claim 1 , wherein a top portion of the through wafer via contacts a bottom portion of the isolation structure.
4. The semiconductor structure of claim 3 , wherein the isolation feature comprises one of:
a trench isolation (TI) structure formed through the shallow trench isolation (STI) structure, and
a deep trench (DT) structure formed below the shallow trench isolation (STI) structure.
5. The semiconductor structure of claim 1 , further comprising a dopant out-diffused from surfaces of a via opening of the through wafer via into the substrate and a deep well.
6. The semiconductor structure of claim 1 , wherein the through wafer via comprises a barrier metal liner around a conductor core.
7. The semiconductor structure of claim 6 , wherein the barrier metal liner comprises an electrically conductive material.
8. The semiconductor structure of claim 7 , wherein the electrically conductive material directly contacts one of the P-well and the N-well.
9. The semiconductor structure of claim 1 , wherein an uppermost surface of the through wafer via contacts a bottommost surface of the isolation structure.
10. The semiconductor structure of claim 1 , wherein the through wafer via directly contacts the isolation structure and avoids direct contact with a source region and a drain region of the NFET device.
11. The semiconductor structure of claim 1 , further comprising a deep N-well in the substrate, wherein the P-well and the N-well are both within the deep N-well.
12. The semiconductor structure of claim 11 , further comprising:
a source/drain region of the NFET device in the P-well and abutting the isolation structure; and
a source/drain region of the PFET device in the N-well and abutting the isolation structure.
13. The semiconductor structure of claim 12 , further comprising an N-well contact in the N-well.
14. The semiconductor structure of claim 11 , wherein the isolation structure extends into the deep N-well.
15. The semiconductor structure of claim 1 , wherein an interface between the substrate contact and a bottom surface of the isolation feature is in a deep N-well.
16. The semiconductor structure of claim 15 , wherein the substrate contact is arranged to prevent formation of a parasitic circuit.
17. A semiconductor structure, comprising:
an NFET device having a P-well at a top side of a substrate;
a PFET device having an N-well at the top side of the substrate;
a substrate contact comprising a through wafer via extending from a backside of the substrate to a bottom surface of an isolation structure located between the NFET device and the PFET device; and
a deep N-well in the substrate.
wherein the P-well and the N-well are both within the deep N-well,
the substrate contact is arranged to prevent formation of a parasitic circuit, and
an interface between the substrate contact and the bottom surface of the isolation structure is in the deep N-well.
18. A semiconductor structure, comprising:
an NFET device having a P-well at a top side of a substrate;
a PFET device having an N-well at the top side of the substrate;
a substrate contact comprising a through wafer via extending from a backside of the substrate to a bottom surface of an isolation structure located between the NFET device and the PFET device; and
a deep N-well in the substrate,
wherein the P-well and the N-well are both within the deep N-well,
the substrate contact is arranged to prevent formation of a parasitic circuit, and
the isolation structure comprises a shallow trench isolation (STI) structure and an isolation feature that abuts and extends below the STI structure.
19. The semiconductor structure of claim 18 , wherein the isolation feature is one of: a trench isolation (TI) structure formed through the STI structure, and a deep trench (DT) structure formed below the STI structure.
20. The semiconductor structure of claim 18 , wherein an interface between the substrate contact and the bottom surface of the isolation feature is in the deep N-well.