IP Library Granted Patent US 9,276,033
Granted Patent B2
US 9,276,033 · App. 14/587,800 · Granted Mar 1, 2016

Semiconductor apparatus, method of manufacturing semiconductor apparatus, method of designing semiconductor apparatus, and electronic apparatus

Inventors: Hiroshi Takahashi (Kanagawa, JP); Shunichi Sukegawa (Kanagawa, JP); Keishi Inoue (Kanagawa, JP)
Assignee: SONY CORPORATION
H01L27/14645H01L21/76802H01L21/76898H01L23/481H01L24/05H01L27/1464H01L27/1469H01L27/14621H01L27/14627H01L27/14632H01L27/14634H01L27/14636H01L27/14638H01L31/02002H01L23/5283H01L23/535H01L2224/02166H01L2224/04042H01L2224/48463H01L2924/1306H01L2924/13091H01L2924/3025
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Quick Facts
Patent No.
US 9,276,033
App. No.
14/587,800
Granted
Mar 1, 2016
Kind
B2
Abstract

A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

Claims (48)

1. A semiconductor device, comprising:

a first material layer including a two-dimensional array area having a plurality of units arranged in a two-dimensional array and a first wiring layer;

a second material layer including a second wiring layer;

a first via passing through the first material layer and reaching a second interconnect provided in the second wiring layer; and

a second via reaching a first interconnect provided in the first wiring layer,

wherein,

an aspect ratio of the first via is smaller than an aspect ratio of the second via.

2. The semiconductor device of claim 1 , further comprising:

a first insulating layer in the first material layer;

a second insulating layer in the second material layer,

wherein,

the first via extends into the second insulating layer in the second material layer, and

the second via extends into the first insulating layer in the first material layer.

3. The semiconductor device of claim 1 , further comprising:

an on chip lens over a photodiode of the first material layer.

4. The semiconductor device of claim 3 , further comprising:

an on chip color filter between the photodiode and the on chip lens.

5. The semiconductor device of claim 1 , wherein the first via has a diameter that is different than a diameter of the second via along a common cross section parallel to an interface between the two material layers.

6. The semiconductor device of claim 1 , wherein the device is a backside illuminated device.

7. The semiconductor device of claim 1 , wherein a photodiode is formed in the first material layer, and wherein the photodiode includes an n-type semiconductor area.

8. The semiconductor device of claim 1 , wherein the second material layer includes a plurality of MOS transistors formed in a p-type semiconductor well area.

9. The semiconductor device of claim 1 , wherein the first via and the second via are located within the two-dimensional array area.

10. The semiconductor device of claim 1 , wherein the second material layer includes a pad layer.

11. The semiconductor device of claim 1 , wherein a topmost layer of the second material layer is an aluminum interconnect layer.

12. The semiconductor device of claim 1 , wherein the second material layer includes signal input and output terminals.

13. The semiconductor device of claim 12 , wherein the signal input and output terminals are located along at least three sides of the second material layer.

14. The semiconductor device of claim 1 , wherein the two-dimensional array area includes a plurality of first and second vias.

15. The semiconductor device of claim 1 , further comprising a photodiode.

16. The semiconductor device of claim 1 , wherein, each of the units in the two-dimensional array region is a photoelectric converter.

17. An electronic apparatus, comprising:

a solid-state imaging apparatus;

an optical system that guides light to the solid-state imaging apparatus;

a signal processing circuit, wherein the signal processing circuit processes an output signal of the solid-state imaging apparatus,

wherein the solid-state imaging apparatus includes:

a first material layer including a two-dimensional array area having a plurality of units arranged in a two-dimensional array and a first wiring layer;

a second material layer including a second wiring layer;

a first via passing through the first material layer and reaching a second interconnect provided in the second wiring layer; and

a second via reaching a first interconnect provided in the first wiring layer,

wherein,

an aspect ratio of the first via is smaller than an aspect ratio of the second via.

18. The electronic apparatus of claim 17 , further comprising:

a first insulating layer in the first material layer;

a second insulating layer in the second material layer,

wherein,

the first via extends into the second insulating layer in the second material layer, and

the second via extends into the first insulating layer in the first material layer.

19. The electronic apparatus of claim 17 , wherein the device is a backside illuminated device.

20. The electronic apparatus of claim 19 , wherein a photodiode is formed in the first material layer, and wherein the photodiode includes an n-type semiconductor area.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2021
From: TAKAHASHI, HIROSHI; SUKEGAWA, SHUNICHI; INOUE, KEISHI
To: SONY CORPORATION
Reel/Frame 056528/0215 →
Priority Claims (1)
JP 2010-070925 · Mar 25, 2010 · national
Continuity (3)
Continuation 13962711 · Aug 8, 2013
Continuation 13050338 · Mar 17, 2011
Related Publication 20150108599A1 · Apr 23, 2015