Protective interface in silicon carbide semiconductor devices
Methods, systems, and devices are disclosed for implementing high power circuits and semiconductor devices. In one aspect, a method for fabricating a silicon carbide (SiC) device includes forming a thin layer of a protection material over a SiC substrate, in which the protection material has a lattice constant that substantially matches a lattice constant of SiC and the thin layer has a thickness of less than a critical layer thickness for the protection material over SiC to form a uniform interface between the protection material and SiC, forming a layer of an insulator material over the thin layer of the protection material, and forming one or more transistor structures over the insulator material.
1. A silicon carbide (SiC) device, comprising:
a SiC substrate;
a thin layer of a protection material formed over the SiC substrate, wherein the protection material has a lattice constant that substantially matches a lattice constant of SiC and the thin layer has a thickness of less than a critical layer thickness for the protection material over SiC to form a uniform interface between the protection material and SiC;
a layer of an insulator material over the thin layer of the protection material; and
one or more transistor structures over the insulator material, wherein the SiC device further comprises:
a metal insulator semiconductor field effect transistor (MISFET) device formed over the SiC substrate,
wherein the MISFET includes
a first electrical contact formed on a first surface of the SiC substrate as one terminal of the MISFET device;
a SiC epitaxial layer formed on a second surface of the SiC substrate opposing the first surface so that the thin layer of the protection material is formed over the SiC epitaxial layer;
a gate contact formed over the layer of the insulator material as a second terminal of the MISFET device;
a doped region formed in the SiC epitaxial layer offset from and near a region in the SiC epitaxial layer under the gate contact; and
a second electrical contact formed over the doped region as a third terminal of the MISFET device.
2. The device as in claim 1 , wherein the protection material includes AlN, the AlN including a lattice constant that differs from a lattice constant of SiC by 1%.
3. The device as in claim 2 , wherein the AlN layer has a thickness less than 4.6 nm and greater than 0.5 nm.
4. The device as in claim 3 , wherein the AlN layer has a thickness less than 2 nm.
5. The device as in claim 3 , wherein the AlN layer has a thickness less than 1 nm.
6. The device as in claim 1 , wherein the insulator material includes silicon oxide.
7. The device as in claim 1 , wherein the first electrical contact is a contact for a drain of the MISFET device and the second electrical contact is a contact for a source of the MISFET device.
8. The device as in claim 1 , wherein the insulator material includes SiO2, Al2O3, TiO2, Ta2O5, HfO2, ZrO2, Y2O3, La2O3, Pr2O3, SiON, or AlON.
9. The device as in claim 1 , wherein the SiC epitaxial layer includes a region configured to provide a contact surface interfacing with the thin layer.