Re-crystallization for boosting stress in MOS device

1. A method comprising: forming a dummy gate stack over a semiconductor substrate; removing the dummy gate stack thereby forming a recess; implanting a portion of the semiconductor substrate through the recess, wherein an amorphous region is formed from the portion of the semiconductor substrate; forming a strained capping layer, wherein the strained capping layer extends into the recess; performing an annealing on the amorphous region to re-crystallize the amorphous region; and then removing the strained capping layer.

2. The method of claim 1 further comprising, after the removing the strained capping layer:

forming a gate dielectric in the recess; and

forming a gate electrode in the recess, wherein the gate electrode is over the gate dielectric.

3. The method of claim 1 , wherein the dummy gate stack comprises a dummy gate dielectric and a dummy gate electrode over the dummy gate dielectric, and wherein after the removing the dummy gate stack, a bottom portion of the dummy gate dielectric remains un-removed.

4. The method of claim 3 further comprising:

after the annealing, removing the bottom portion of the dummy gate dielectric.

5. The method of claim 1 further comprising:

forming a source/drain region adjacent to the dummy gate stack, wherein the source/drain region is of p-type, and wherein the strained capping layer applies a compressive stress to the portion of the semiconductor substrate.

6. The method of claim 1 further comprising:

forming a source/drain region adjacent to the dummy gate stack, wherein the source/drain region is of n-type, and wherein the strained capping layer applies a tensile stress to the portion of the semiconductor substrate.

7. The method of claim 1 further comprising:

forming a contact etch stop layer overlying the dummy gate stack;

forming an inter-layer dielectric over the contact etch stop layer; and

performing a planarization to remove portions of the contact etch stop layer and the inter-layer dielectric over the dummy gate stack.

8. A method comprising: forming a dummy gate stack over a semiconductor substrate; removing the dummy gate stack to form a recess; forming a source region and a drain region in the semiconductor substrate, wherein the source region and the drain region are on opposite sides of the dummy gate stack; implanting a portion of the semiconductor substrate through the recess to amorphize a portion of the semiconductor substrate, wherein an amorphous region is formed from the portion of the semiconductor substrate; forming a strained capping layer, wherein a portion of the strained capping layer extends into the recess, with a portion of the recess remaining after the strained capping layer is formed; performing an annealing on the amorphous region to re-crystallize the amorphous region; and then removing the strained capping layer.

9. The method of claim 8 further comprising: wherein the forming the strained capping layer is performed after the implanting and before the annealing.

10. The method of claim 9 , wherein the source region and the drain region are of p-type, and wherein the strained capping layer applies a compressive stress to the amorphous region.

11. The method of claim 9 , wherein the source region and the drain region are of n-type, and wherein the strained capping layer applies a tensile stress to the amorphous region.

12. The method of claim 8 , wherein the dummy gate stack comprises a dummy gate dielectric and a dummy gate electrode over the dummy gate dielectric, and wherein in the removing the dummy gate stack, a bottom portion of the dummy gate dielectric remains un-removed.

13. The method of claim 12 further comprising:

after the annealing, removing the bottom portion of the dummy gate dielectric.

14. A method comprising:

forming a dummy gate stack over a semiconductor substrate;

forming a source/drain region in the semiconductor substrate, wherein the source/drain region is adjacent to the dummy gate stack;

forming a contact etch stop layer overlying the dummy gate stack and the source/drain region;

forming an inter-layer dielectric over the contact etch stop layer;

performing a chemical mechanical polish to expose the dummy gate stack;

removing the dummy gate stack to form a recess in the inter-layer dielectric;

implanting a portion of the semiconductor substrate through the recess, wherein an amorphous region is formed from the portion of the semiconductor substrate;

forming a strained capping layer over the inter-layer dielectric;

performing an annealing on the amorphous region to re-crystallize the amorphous region;

after the annealing, removing the strained capping layer;

forming a gate dielectric in the recess; and

forming a gate electrode in the recess, wherein the gate electrode is over the gate dielectric.

15. The method of claim 14 , wherein the source/drain region is of p-type, and wherein the strained capping layer applies a compressive stress to the amorphous region.

16. The method of claim 14 , wherein the source/drain region is of n-type, and wherein the strained capping layer applies a tensile stress to the portion of the semiconductor substrate.

17. The method of claim 14 , wherein the dummy gate stack comprises a dummy gate dielectric and a dummy gate electrode over the dummy gate dielectric, and wherein in the removing the dummy gate stack, a bottom portion of the dummy gate dielectric remains un-removed.

18. The method of claim 14 , wherein the strained capping layer extends into the recess.

19. The method of claim 1 , wherein the strained capping layer fills the recess partially.

20. The method of claim 14 , wherein the strained capping layer extends to a bottom and sidewalls of the recess, and wherein a top portion of the recess is unfilled with the strained capping layer.