Embedded memory and power management subpackage
Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.
1. A package assembly comprising:
a subpackage having a first side and a second side disposed opposite to the first side, the subpackage including:
one or more package-level interconnect contacts disposed on the first side the subpackage; and
a first die having a first side and a second side disposed opposite to the first side, the first side of the first die being disposed between the second side of the first die and the first side of the subpackage; and
a second die having a first side and a second side disposed opposite to the first side, the first side of the second die being coupled to the second side of the subpackage and electrically coupled to the second side of the first die, wherein a first portion of the first die is within an area defined b extension of a perimeter of the second die in a direction perpendicular to the first side of the second die, wherein a second portion of the first die extends outside of the area defined by the extension of the perimeter of the second die in the direction perpendicular to the first side of the second die, wherein the subpackage includes one or more conductive pathways located between the second side of the first die and the second side of the subpackage, and wherein the one or more conductive pathways are coupled to the second portion of the first die that extends outside of the area defined by the extension of the perimeter of the second die in the direction perpendicular to the first side of the second die.
2. The package assembly of claim 1 , wherein:
the first die includes a memory die and the second die includes a central processing unit (CPU).
3. The package assembly of claim 2 , wherein:
the first die is embedded in a mold core of the subpackage and the subpackage includes one or more build-up layers coupled with the mold core on the second side of the subpackage including conductive pathways for electrically coupling the second die to the first side of the first die.
4. The package assembly of claim 1 , wherein:
the second die is electrically coupled to the second side of the first die in the first portion of the first die.
5. The package assembly of claim 4 , wherein:
the second die is directly electrically coupled to the second side of the first die using die-level interconnects.
6. The package assembly of claim 5 wherein:
the first die is configured to receive power through the second die.
7. The package assembly of claim 1 , wherein:
the second die is electrically coupled to at least one of the one or more package-level interconnect contacts by conductive pathways that connect the second side of the subpackage to the first side of the subpackage.
8. The package assembly of claim 1 , comprising:
a third die at least partially embedded in the subpackage, the third die having a first side and a second side disposed opposite to the first side;
wherein a portion of the third die is within the area defined by the extension of the perimeter of the second die in the direction perpendicular to the first side of the second die.
9. A computing device comprising:
a circuit board;
a subpackage having a first side and a second side disposed opposite to the first side, the first side being coupled with the circuit board using one or more package-level interconnects disposed on the first side of the subpackage, the subpackage including:
a first die having a first side and a second side disposed opposite to the first side, the first side of the first die being disposed between the second side of the first die and the first side of the subpackage; and
a second die having a first side and a second side disposed opposite to the first side, the first side of the second die being coupled to the second side of the subpackage and electrically coupled to the second side of the first die, wherein a first portion of the first die is within an area defined b extension of a perimeter of the second die in a direction perpendicular to the first side of the second die, wherein a second portion of the first die extends outside of the area, wherein the subpackage includes one or more conductive pathways located between the second side of the first die and the second side of the subpackage, and wherein the one or more conductive pathways are coupled to the second portion of the first die.
10. The computing device of claim 9 , wherein:
the second die is directly electrically coupled to the second side of the first die.
11. The computing device of claim 9 , wherein:
the second die is electrically coupled to the second side of the first die in the first portion of the first die.
12. The computing device of claim 9 , wherein:
the computing device is a mobile computing device including one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board.
13. The package assembly of claim 1 , wherein the one or more conductive pathways electrically couple the first side of the second die to the second side of the first die.
14. The package assembly of claim 1 , wherein the subpackage further includes an additional layer located between the second side of the subpackage and the second side of the first die, wherein the one or more conductive pathways are formed in the additional layer.
15. The package assembly of claim 1 , wherein the one or more conductive pathways couple the second side of the first die to a first end of a pass through via.
16. The package assembly of claim 15 , wherein a second end of the pass through via, opposite the first end, is coupled to the one or more package-level interconnect contacts, and wherein the first die is electrically coupled to the one or more package-level interconnect contacts by the pass through via.
17. The computing device of claim 9 , wherein the one or more conductive pathways electrically couple the first side of the second die to the second side of the first die.
18. The computing device of claim 9 , wherein the one or more conductive pathways couple the second side of the first die to a first end of a pass through via.
19. The computing device of claim 18 , wherein a second end of the pass through via, opposite the first end, is coupled to the circuit board by the one or more package-level interconnects, and wherein the first die is electrically coupled to the circuit board by the pass through via.
20. The computing device of claim 9 , wherein the subpackage further includes an additional layer located between the second side of the subpackage and the second side of the first die, wherein the one or more conductive pathways are formed in the additional layer.