Semiconductor memory device and method for manufacturing the same
A highly integrated DRAM is provided. A bit line is formed over a first insulator, a second insulator is formed over the bit line, third insulators which are in a stripe shape and the like are formed over the second insulator, and a semiconductor region and a gate insulator are formed to cover one of the third insulators. The bit line is connected to the semiconductor region through first contact plugs. Then, a conductive film is formed and subjected to anisotropic etching to form word lines at side surfaces of the third insulators, and a second contact plug is formed to be connected to a capacitor at a top of the one of the third insulators. By synchronizing the word lines, electric charge is accumulated or released through the capacitor. With such a structure, the area of a memory cell can be 4F 2 .
1. A semiconductor memory device comprising:
a bit line over a substrate;
contact plugs over the bit line;
an insulator over the contact plugs;
a conductive layer over and in contact with a top surface of the insulator;
a semiconductor layer over and in contact with the conductive layer and the contact plugs;
a first word line and a second word line adjacent to side surfaces of the insulator with the semiconductor layer interposed therebetween; and
a capacitor electrically connected to the conductive layer,
wherein a thickness of each of the first word line and the second word line is greater than or equal to 40% and less than or equal to 80% of a sum of thicknesses of the insulator and the conductive layer.
2. The semiconductor memory device according to claim 1 , wherein the semiconductor layer is electrically connected to the bit line.
3. The semiconductor memory device according to claim 1 , wherein a thickness of the insulator is greater than or equal to twice and less than or equal to 20 times a width thereof.
4. The semiconductor memory device according to claim 1 , further comprising a driver circuit below the bit line.
5. The semiconductor memory device according to claim 1 , wherein the semiconductor layer is a material with a band gap of greater than or equal to 2.5 eV and less than or equal to 4 eV.
6. The semiconductor memory device according to claim 1 , wherein the semiconductor layer comprises an oxide semiconductor.
7. The semiconductor memory device according to claim 1 , wherein the same signal is applied to the first and second word lines.
8. A semiconductor device comprising:
a first conductive layer;
a first insulating layer over the first conductive layer;
contact plugs in the first insulating layer;
a second insulating layer over the contact plugs, and over and in direct contact with the first insulating layer;
a second conductive layer over and in contact with a top surface of the second insulating layer;
an oxide semiconductor layer over and in contact with the second conductive layer and the contact plugs;
a third insulating layer adjacent to the second insulating layer with the oxide semiconductor layer interposed therebetween;
a third conductive layer adjacent to a first side surface of the second insulating layer with the oxide semiconductor layer and the third insulating layer interposed therebetween; and
a fourth conductive layer adjacent to a second side surface of the second insulating layer with the oxide semiconductor layer and the third insulating layer interposed therebetween,
wherein the oxide semiconductor layer includes a channel formation region,
wherein the oxide semiconductor layer is electrically connected to the first conductive layer, and
wherein a thickness of each of the third conductive layer and the fourth conductive layer is greater than or equal to 40% and less than or equal to 80% of a sum of thicknesses of the second insulating layer and the second conductive layer.
9. The semiconductor device according to claim 8 ,
wherein the first conductive layer is a bit line, and
wherein each of the third conductive layer and the fourth conductive layer is a word line.
10. The semiconductor device according to claim 8 , further comprising a capacitor,
wherein the capacitor is electrically connected to the second conductive layer.
11. A semiconductor device comprising:
a first conductive layer;
a first insulating layer over the first conductive layer;
contact plugs in the first insulating layer;
a second insulating layer over the contact plugs, and over and in direct contact with the first insulating layer;
a second conductive layer over and in contact with a top surface of the second insulating layer;
an oxide semiconductor layer over and in contact with the second conductive layer and the contact plugs;
a third insulating layer adjacent to the second insulating layer with the oxide semiconductor layer interposed therebetween; and
a third conductive layer adjacent to a side surface of the second insulating layer with the oxide semiconductor layer and the third insulating layer interposed therebetween,
wherein the oxide semiconductor layer includes a channel formation region,
wherein the oxide semiconductor layer is electrically connected to the first conductive layer, and
wherein a thickness of the third conductive layer is greater than or equal to 40% and less than or equal to 80% of a sum of thicknesses of the second insulating layer and the second conductive layer.
12. The semiconductor device according to claim 11 ,
wherein the first conductive layer is a bit line, and
wherein the third conductive layer is a word line.
13. The semiconductor device according to claim 11 , further comprising a capacitor,
wherein the capacitor is electrically connected to the second conductive layer.