IP Library Granted Patent US 9,287,405
Granted Patent B2
US 9,287,405 · App. 13/632,603 · Granted Mar 15, 2016

Semiconductor device comprising oxide semiconductor

Inventors: Shinya Sasagawa (Chigasaki, JP); Motomu Kurata (Isehara, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/78606H01L27/1156H01L29/66969H01L29/7869
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Quick Facts
Patent No.
US 9,287,405
App. No.
13/632,603
Granted
Mar 15, 2016
Kind
B2
Abstract

A miniaturized transistor having excellent electrical characteristics is provided with high yield. Further, a semiconductor device including the transistor and having high performance and high reliability is manufactured with high productivity. In a semiconductor device including a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions between which the channel formation region is sandwiched, a gate insulating film, and a gate electrode layer whose top surface and side surface are covered with an insulating film including an aluminum oxide film are stacked, a source electrode layer and a drain electrode layer are in contact with part of the oxide semiconductor film and the top surface and a side surface of the insulating film including an aluminum oxide film.

Claims (21)

1. A semiconductor device comprising:

an oxide semiconductor film over an oxide insulating film;

a gate insulating film over the oxide semiconductor film;

a gate electrode layer over the gate insulating film overlapping with the oxide semiconductor film;

an insulating film including an aluminum oxide film covering an entire top surface and an entire side surface of the gate electrode layer;

an interlayer insulating layer over the oxide semiconductor film, the gate insulating film, the gate electrode layer, and the insulating film including the aluminum oxide film, wherein an opening reaching the oxide semiconductor film is provided in the interlayer insulating layer; and

a wiring layer in contact with the oxide semiconductor film and a top surface and a side surface of the insulating film including the aluminum oxide film, the wiring layer being provided in the opening,

wherein the interlayer insulating layer is in contact with a top surface and a side surface of the oxide semiconductor film and the top surface of the insulating film including the aluminum oxide film, and

wherein the insulating film including the aluminum oxide film is in contact with the top surface of the oxide semiconductor film.

2. The semiconductor device according to claim 1 ,

wherein the oxide semiconductor film comprises a channel formation region and low-resistance regions between which the channel formation region is sandwiched, and

wherein each of the low-resistance regions includes a dopant.

3. The semiconductor device according to claim 1 , wherein an oxygen concentration in a region overlapping with the gate electrode layer and the insulating film including the aluminum oxide film in the oxide semiconductor film is higher than an oxygen concentration in a region other than the region overlapping with the gate electrode layer and the insulating film including the aluminum oxide film in the oxide semiconductor film.

4. The semiconductor device according to claim 1 , further comprising an electrode layer below the oxide semiconductor film,

wherein the electrode layer is in contact with the oxide semiconductor film and overlaps with the wiring layer.

5. The semiconductor device according to claim 1 , further comprising an electrode layer below the oxide semiconductor film,

wherein the electrode layer is in contact with the oxide semiconductor film and overlaps with the wiring layer, and

wherein the electrode layer is provided over the oxide insulating film.

6. The semiconductor device according to claim 1 , further comprising an electrode layer below the oxide semiconductor film,

wherein the electrode layer is in contact with the oxide semiconductor film and overlaps with the wiring layer, and

wherein the electrode layer is embedded in the oxide insulating film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2012
From: SASAGAWA, SHINYA; KURATA, MOTOMU
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 029055/0816 →
Priority Claims (1)
JP 2011-226080 · Oct 13, 2011 · national
Continuity (1)
Related Publication 20130092924A1 · Apr 18, 2013