Quantum dot channel (QDC) quantum dot gate transistors, memories and other devices
This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories.
1. A quantum dot channel (QDC) field-effect transistor device, comprising:
a substrate, wherein the substrate includes
a source region,
a gate region,
a drain region, and
a transport channel located between the source region and the drain region,
wherein the transport channel is comprised of an array of cladded quantum dots, the cladded quantum dots being comprised of at least one Si and Ge and having a thin cladding layer comprised of at least one of SiOx and GeOx, and
wherein the array of cladded quantum dots include a top layer of cladded quantum dots and a bottom layer of cladded quantum dots, the array of cladded quantum dots being assembled on a semiconductor substrate of p-type conductivity and being constructed from a semiconductor material which includes at least one of Si, Ge, InGaAs, GaAs, GaN,
wherein the array of cladded quantum dots are deposited in a region between source region and the drain region, and wherein the cladding of the top layer of cladded quantum dots is deposited with a thin gate insulator layer,
wherein the thin gate insulator layer is deposited with a gate material constructed from at least one of a metallic material and a semiconducting material which results in a pre-determined threshold voltage for the field-effect transistor.
2. A field effect transistor, configured as a nonvolatile random access memory, the field effect transistor comprising:
a source region,
a gate region,
a drain region, and
a transport channel region located between the source region and the drain region,
wherein the gate region includes a first thin gate insulator layer deposited with a first set of cladded quantum dots over the transport channel region, and
wherein the first set of cladded quantum dots is deposited with a second set of cladded quantum dots having a thin cladding layer, the first set of cladded quantum dots forming a floating gate which stores a charge when a memory is written, and
wherein the second set of cladded quantum dots include a thin barrier and a small core to transport charge, wherein a top part of the second set of cladded quantum dots is deposited with a second gate insulator over the transport channel region,
wherein a first gate is formed over the first set of cladded quantum dots and the second set of cladded quantum dots,
wherein the first gate is disposed over the transport channel region, and wherein the second set of cladded quantum dots are contacted by a second gate which is located differently from the first gate, wherein the second gate is formed in a region where the gate insulator is relatively thicker then the first gate insulator, and
wherein the second gate is used to extract electrons deposited on the quantum dot floating gate during an erase cycle, wherein the electrons may be removed by biasing the second gate and the source region.
3. The field effect transistor of claim 2 , where the transport channel is comprised of array of cladded quantum dots, comprising at least one layer of cladded quantum dots.
4. A quantum dot channel (QDC) field-effect transistor device, comprising:
a source region,
a gate region,
a drain region, and
a transport channel region, wherein the transport channel region is located between the source region and the drain region,
wherein the transport channel region includes an array of cladded quantum dots, the cladded quantum dots being comprised of at least one Si and Ge and having a thin cladding layer comprised of at least one of SiOx and GeOx, and
wherein the array of cladded quantum dots include a cladded quantum dot top layer and a cladded quantum dot bottom layer, the array of cladded quantum dots being assembled on a semiconductor substrate and being at least partially constructed from a semiconductor material which includes at least one of Si, Ge, InGaAs, GaAs, GaN, amorphous Si-on-glass, amorphous SiGe-on-glass, amorphous-Ge-on-glass, amorphous-InGaZnO-on-glass, amorphous-Si-on-sapphire,
wherein the array of cladded quantum dots are deposited between the source region and the drain region, and wherein the cladded quantum dot top layer includes a cladding deposited with a thin gate insulator layer, and
wherein the thin gate insulator layer is deposited with a gate material constructed from at least one of a metallic material and a semiconducting material which results in a pre-determined threshold voltage for the field-effect transistor.
5. The quantum dot channel (QDC) field-effect transistor device of claim 4 , wherein the semiconductor substrate is at least one of a p-type substrate and an n-type substrate.
6. A field effect transistor, wherein the field effect transistor is configured as a nonvolatile random access memory, the field effect transistor comprising:
a substrate having a,
a source region,
a gate region,
a first drain region, and
a transport channel region, wherein the transport channel region is located between the source region and the first drain region,
wherein the gate region includes a first thin gate insulator layer deposited with a first set of cladded quantum dots, and
wherein the first set of cladded quantum dots is deposited with a second set of cladded quantum dots having a cladding layer, the first set of cladded quantum dots forming a floating gate configured to store a charge, and
wherein the second set of cladded quantum dots include a top portion deposited with a second gate insulator over the transport channel region an including an overlap outside the transport channel region,
wherein the gate region is formed over the second gate insulator and disposed over the transport channel region, and
wherein the second set of cladded quantum dots are contacted by a second drain region which is located differently from the first drain region, wherein the second drain region is formed in a region where the second gate insulator has a different thickness then the first gate insulator, and
wherein the second drain region is configured to extract electrons deposited on the floating gate by biasing the second drain region and the source region.