Apparatus and method for power MOS transistor

1. An apparatus comprising:

a first epitaxial layer over a first side of a substrate;

a second epitaxial layer over the first epitaxial layer;

a first drain/source contact plug formed over the second epitaxial layer, wherein the first drain/source contact plug is coupled to a first drain/source region, and wherein the first drain/source region is between the first drain/source contact plug and the second epitaxial layer;

a second drain/source contact plug formed below a second side of the substrate, wherein the second drain/source contact plug is coupled to a second drain/source region, and wherein the first side is opposite to the second side;

a trench formed in the first drain/source region, the second epitaxial layer and the first epitaxial layer, and extending from a top surface of the first drain/source region to a bottom portion of the first epitaxial layer, wherein a bottom surface of the trench is in direct contact with a top surface of the second drain/source region;

a gate electrode in a lower portion of the trench; and

a field plate surrounded by the gate electrode, wherein the field plate is electrically coupled to the second drain/source region, and wherein the second drain/source region is connected to the second drain/source contact plug through a low resistance path including the field plate.

2. The apparatus of claim 1 , further comprising:

a drain drift region formed along sidewalls of a middle portion of the trench, wherein the trench is surrounded by the drain drift region.

3. The apparatus of claim 1 , wherein:

the first epitaxial layer is a p-type epitaxial layer formed over the substrate, and wherein a bottom surface of the p-type epitaxial layer is in direct contact with a top surface of the substrate; and

a portion of a p+ region formed in the p-type epitaxial layer, wherein the p+ region is electrically coupled to the field plate, wherein a doping density of the p+ region is different from a doping density of the p-type epitaxial layer.

4. The apparatus of claim 3 , wherein:

the second drain/source region is an n+ region formed between the gate electrode and the p+ region.

5. The apparatus of claim 4 , wherein the n+ region is coupled to the second drain/source contact plug through the field plate, the p+ region and the substrate.

6. The apparatus of claim 1 , further comprising:

a dielectric film formed between the gate electrode and the field plate.

7. The apparatus of claim 6 , wherein:

the dielectric film is formed of an oxide and have a thickness in a range from about 0.1 um to about 0.5 um.

8. The apparatus of claim 1 , wherein:

the first drain/source region is a drain of a trench power transistor; and

the second drain/source region is a source of the trench power transistor.

9. A device comprising:

a drain region formed over a substrate;

a source region formed over the substrate, wherein a bottom surface of the drain region is higher than a top surface of the source region; and

a trench formed in the drain region and epitaxial layers between the drain region and the substrate, and extending from the drain region to the source region;

a gate electrode in the trench; and

a field plate formed adjacent to the gate electrode, wherein the gate electrode and the field plate are separated by a dielectric film, and wherein the field plate is electrically coupled to and in direct contact with the source region.

10. The device of claim 9 , further comprising:

a drain-drift region coupled to the drain region, wherein the trench is surrounded by the drain drift region.

11. The device of claim 9 , further comprising:

a first epitaxial layer formed over the substrate, wherein a bottom surface of the first epitaxial layer is in direct contact with a top surface of the substrate; and

a second epitaxial layer formed over the first epitaxial layer, wherein a conductivity type of the second epitaxial layer is different from a conductivity type of the first epitaxial layer.

12. The device of claim 9 , further comprising:

a drain contact plug coupled to the drain region, wherein the drain contact plug is formed over a first side of the substrate; and

a source contact plug coupled to the source region, wherein the source contact plug is formed over a second side of the substrate, wherein the second side is opposite to the first side.

13. A structure comprising:

a first epitaxial layer on a substrate;

a source region in the first epitaxial layer;

a second epitaxial layer on the first epitaxial layer;

a drain region in the second epitaxial layer over;

a trench formed in the drain region, the second epitaxial layer and the first epitaxial layer, and extending from the drain region to a bottom portion of the first epitaxial layer;

a gate electrode in the trench; and

a field plate adjacent to the gate electrode, wherein the gate electrode and the field plate are separated by a dielectric film, and wherein the field plate is electrically coupled to and in direct contact with the source region.

14. The structure of claim 13 , further comprising:

a source contact plug underlying the substrate; and

a drain contact plug overlying the drain region.

15. The structure of claim 13 , wherein:

the substrate is of a first conductivity type;

the first epitaxial layer is of the first conductivity type; and

the second epitaxial layer is of a second conductivity type.

16. The structure of claim 13 , wherein:

the substrate is of a first conductivity type;

the source region is of a second conductivity type; and

the drain region is of the second conductivity type.

17. The structure of claim 13 , further comprising:

a drain-drift region coupled to the drain region.