Method of fabricating array substrate
A method of fabrication an array substrate includes forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing hydrogen plasma treatment; forming barrier layers on the source and drain areas, the barrier layer having a first thickness; forming an inter insulating layer on the gate electrode and having first contact holes that expose the barrier layers; and forming source and drain electrodes on the inter insulating layer and contacting the barrier layers through the first contact holes, respectively.
1. A method of fabrication an array substrate, the method comprising:
forming an oxide semiconductor layer on a substrate;
sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer;
forming source and drain areas having conductive properties in the oxide semiconductor layer by performing hydrogen plasma treatment;
forming barrier layers on the source and drain areas, the barrier layer having a first thickness;
forming an inter insulating layer on the gate electrode and having first contact holes that expose the barrier layers; and
forming source and drain electrodes on the inter insulating layer and contacting the barrier layers through the first contact holes, respectively,
wherein the barrier layers are formed in direct contact with sides and upper surfaces of the gate electrode and the source and drain areas.
2. The method according to claim 1 , wherein the barrier layers include an almost inoxidizable metallic material selected from cobalt (Co), nickel (Ni), gold (Au) and silver (Ag).
3. The method according to claim 1 , wherein the barrier layers are formed by one of a plating method, a chemical vapor deposition method of a metallic material, and an atom layer deposition method.
4. The method according to claim 1 , wherein the first thickness is within a range of several angstroms to dozen angstroms.
5. The method according to claim 1 , wherein the oxide semiconductor layer includes one of indium gallium zinc oxide, zinc tin oxide, and zinc indium oxide.
6. The method according to claim 1 , further comprising:
forming a passivation layer on the source and drain electrodes and having a second contact hole exposing the drain electrode; and
forming a pixel electrode on the passivation layer and contacting the drain electrode through the second contact hole.